公开(公告)号：US11928069B2

公开(公告)日：2024-03-12

申请号：US17422666

申请日：2019-01-15

Applicant: Christoph Heldeis

Inventor： Christoph Heldeis

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/4022

Abstract: An optical output device is described that includes one bus system. The bus system includes two bus wires of a bus, two bus units and one bus control unit. The two bus units may include one optical output element one output control unit whose output is connected to the one optical output element a first storage unit for storing address data of the respective bus unit a second storage unit for storing a counter value, a comparison unit whose inputs are connected to the first storage unit and to the second storage unit, and a control unit whose input is connected to an output of the comparison unit and which controls the takeover of data from the bus into the output control unit depending on an output signal or on output data of the comparison unit.

公开(公告)号：US11921905B2

公开(公告)日：2024-03-05

申请号：US17046535

申请日：2018-07-18

Applicant: Google LLC

Inventor： Uday Savagaonkar ,  Eric Northup

IPC: G06F21/72 ,  G06F13/42 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F21/72 ,  G06F13/4221 ,  G06F21/602 ,  G06F21/79 ,  G06F2213/0026

Abstract: Aspects of the disclosure relate to providing a secure collaboration between one or more PCIe accelerators and an enclave. An example system may include a PCIe accelerator apparatus. The PCIs accelerator apparatus may include the one or more PCIe accelerators and a microcontroller configured to provide a cryptographic identity to the PCIe accelerator apparatus. The PCIe accelerator apparatus may be configured to use the cryptographic identity to establish communication between the PCIe accelerator apparatus the enclave.

公开(公告)号：US11921660B2

公开(公告)日：2024-03-05

申请号：US17827271

申请日：2022-05-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jiang Zhu ,  Fei Luo ,  Jiankang Li ,  Yulong Ma

IPC: G06F13/40 ,  G06F13/362 ,  G06F13/42

CPC classification number: G06F13/362 ,  G06F13/4022 ,  G06F13/4221

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

公开(公告)号：US11921659B2

公开(公告)日：2024-03-05

申请号：US18151717

申请日：2023-01-09

Applicant: Liqid Inc.

Inventor： James Scott Cannata ,  Christopher R. Long ,  Sumit Puri ,  Bryan Schramm

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4234 ,  G06F2213/0026

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a management processor configured to initiate a communication arrangement between a first endpoint device coupled to a communication fabric and a second endpoint device coupled to the communication fabric. The communication arrangement is configured to redirect a transfer from the first endpoint device based on an address corresponding to an address range of the second endpoint device without passing the transfer through a host processor coupled to the communication fabric that executes an application initiating the transfer.

公开(公告)号：US11916781B2

公开(公告)日：2024-02-27

申请号：US17594624

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Partha Pratim Kundu ,  David Charles Hewson

IPC: H04L49/9005 ,  H04L49/90 ,  H04L49/9047 ,  G06F13/40 ,  H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  G06F13/38 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625 ,  H04L69/28

CPC classification number: H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/626 ,  H04L47/629 ,  H04L47/6235 ,  H04L47/6275 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of efficiently utilizing an output buffer is provided. The NIC can be equipped with an output buffer, a host interface, an injector logic block, and an allocation logic block. The output buffer can include a plurality of cells, each of which can be a unit of storage in the output buffer. If the host interface receives a command from a host device, the injector logic block can generate a packet based on the command. The allocation logic block can then determine whether the packet is a multi-cell packet. If the packet is a multi-cell packet, the allocation logic block can determine a virtual index for the packet. The allocation logic block can then store, in an entry in a data structure, the virtual index, and a set of physical indices of cells storing the packet.

公开(公告)号：US11907035B2

公开(公告)日：2024-02-20

申请号：US16875898

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Ang Li ,  David J. Harriman ,  Kuan Hua Tan

IPC: G06F1/28 ,  G06F13/42 ,  G06F1/04

CPC classification number: G06F1/28 ,  G06F1/04 ,  G06F13/4221 ,  G06F13/4295 ,  G06F2213/0026

Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.

公开(公告)号：US20240056385A1

公开(公告)日：2024-02-15

申请号：US18491879

申请日：2023-10-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Abdulla M. Bataineh ,  Jonathan Paul Beecroft ,  Thomas L. Court ,  Anthony M. Ford ,  Edwin L. Froese ,  David Charles Hewson ,  Joseph Kopnick ,  Andrew Kopser ,  Duncan Roweth ,  Gregory Faanes ,  Michael Higgins ,  Timothy J. Johnson ,  Trevor Jones ,  James Reinhard ,  Edward J. Turner ,  Steven L. Scott

IPC: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625

CPC classification number: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/22 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/30 ,  H04L69/40 ,  H04L47/39 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/1673 ,  G06F13/1689 ,  H04L45/021 ,  H04L45/38 ,  H04L47/12 ,  G06F13/1642 ,  G06F13/4221 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/621 ,  H04L47/24 ,  H04L49/9021 ,  G06F13/16 ,  G06F13/385 ,  G06F13/4022 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L45/123 ,  H04L47/122 ,  H04L45/566 ,  G06F12/1036 ,  G06F15/17331 ,  H04L49/90 ,  H04L43/10 ,  H04L45/20 ,  H04L45/42 ,  H04L47/11 ,  H04L47/18 ,  G06F12/0862 ,  G06F12/1063 ,  H04L47/323 ,  G06F9/546 ,  G06F13/14 ,  G06F9/505 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  G06F13/4068 ,  H04L47/6235 ,  H04L47/762 ,  H04L47/781 ,  H04L47/20 ,  H04L49/9036 ,  H04L49/9047 ,  H04L1/0083 ,  H04L43/0876 ,  H04L45/46 ,  H04L45/70 ,  H04L47/2466 ,  H04L47/626 ,  H04L47/32 ,  G06F2213/0026 ,  G06F2213/3808 ,  G06F2212/50 ,  H04L69/28

Abstract: A switch architecture for a data-driven intelligent networking system is provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.

公开(公告)号：US11900003B2

公开(公告)日：2024-02-13

申请号：US17559863

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Srikanth Kambhatla

IPC: G06F3/14 ,  G06F13/40 ,  G06F13/42 ,  H04L65/61 ,  H04L65/1089 ,  G09G5/00 ,  H04L43/0882

CPC classification number: G06F3/1423 ,  G06F13/4027 ,  G06F13/4221 ,  G09G5/006 ,  H04L65/1089 ,  H04L65/61 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/20 ,  H04L43/0882

Abstract: A disclosed example involves receiving a message with an action to be performed; determining the message type; and based on the message type, performing an action specified in the message.

公开(公告)号：US11899593B2

公开(公告)日：2024-02-13

申请号：US17557363

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Przemyslaw Duda

IPC: G06F12/1081 ,  G06F12/02 ,  G06F12/14 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F12/1081 ,  G06F12/0238 ,  G06F12/1425 ,  G06F13/1673 ,  G06F13/4221

Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes a computer-readable memory for storage of data, the computer-readable memory comprising a first memory buffer and a second memory buffer, an attack discovery unit device comprising processing circuitry to perform operations, comprising, receiving a direct memory access (DMA) request from a remote device via a Peripheral Component Interconnect Express (PCIe) link, the direct memory access (DMA) request comprising a host physical address and a header indicating that the target memory address has previously been translated to a host physical address (HPA), and blocking a direct memory access in response to a determination of at least one of that the remote device has not obtained a valid address translation from a translation agent, or that the remote device has not obtained a valid translation for the target memory address from the translation agent.

公开(公告)号：US11886358B2

公开(公告)日：2024-01-30

申请号：US17717452

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Balint Fleischer

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06 ,  G06F12/02 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F12/0246 ,  G06F12/063 ,  G06F13/4068 ,  G06F13/4221

Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.