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    Equalization time configuration method, chip, and communications system
    1.
    发明授权
    Equalization time configuration method, chip, and communications system 有权

    公开(公告)号：US11347669B2

    公开(公告)日：2022-05-31

    申请号：US16952350

    申请日：2020-11-19

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yongyao Li ,  Jiang Zhu ,  Fei Luo ,  Jiankang Li ,  Yulong Ma

    IPC: G06F13/362 ,  G06F13/40 ,  G06F13/42

    Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

    Equalization training method and apparatus, and system
    3.
    发明授权
    Equalization training method and apparatus, and system 有权

    公开(公告)号：US12095597B2

    公开(公告)日：2024-09-17

    申请号：US18070986

    申请日：2022-11-29

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Yongyao Li ,  Fei Luo ,  Jiang Zhu

    IPC: H04L25/03

    CPC classification number: H04L25/03885

    Abstract: An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. According to this method, an equalization timeout period used for equalization training can be flexibly configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to better ensure that an equalization parameter is found within the configured equalization timeout period, thereby improving an equalization training success rate.

    Signal transmission method and system and retimer
    5.
    发明授权
    Signal transmission method and system and retimer 有权

    公开(公告)号：US10958413B2

    公开(公告)日：2021-03-23

    申请号：US16533365

    申请日：2019-08-06

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yongyao Li ,  Jiankang Li ,  Jun Yu ,  Jiang Zhu ,  Fei Luo

    IPC: H03H7/30 ,  H04L7/033 ,  H04L1/00 ,  H04L7/00 ,  H04L25/03 ,  H04L29/06

    Abstract: A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.

    DQS Position Adjustment Method , Controller and Network Device
    6.
    发明申请
    DQS Position Adjustment Method , Controller and Network Device 有权

    公开(公告)号：US20210065757A1

    公开(公告)日：2021-03-04

    申请号：US17097680

    申请日：2020-11-13

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yongyao Li ,  Jun Yu ,  Guoyu Wang ,  Jiankang Li ,  You Li ,  Ruihui Hong

    IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076

    Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

    Memory training method, memory controller, processor, and electronic device
    7.
    发明授权
    Memory training method, memory controller, processor, and electronic device 有权

    公开(公告)号：US12174763B2

    公开(公告)日：2024-12-24

    申请号：US18192019

    申请日：2023-03-29

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Nianbing Li ,  Yongyao Li ,  Zhongjian Chen ,  Shibin Xu ,  Liangyi Zhang

    IPC: G06F13/16

    Abstract: This application provides a memory training method, a memory controller, a processor, and an electronic device. The memory controller keeps transmission delays of N DQs unchanged, adjusts a transmission delay of a DQS, and determines a maximum DQS transmission delay and/or a minimum DQS transmission delay of the DQS when all data carried in the N DQs is correctly transmitted. The memory controller adjusts the transmission delay of the DQS to a target DQS transmission delay between the maximum DQS transmission delay and the minimum DQS transmission delay. The method helps quickly align relative timing positions between the DQS and the N DQs. Therefore, memory training may be repeatedly performed in a working process of the processor, so that the N DQs keep long enough timing margins.

    Drive and data transmission method
    9.
    发明授权
    Drive and data transmission method 有权

    公开(公告)号：US11973856B2

    公开(公告)日：2024-04-30

    申请号：US17321707

    申请日：2021-05-17

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Yongyao Li ,  Fei Luo ,  Jiankang Li ,  Jiang Zhu ,  Jieping Zeng

    IPC: H04L7/00 ,  G06F13/42

    CPC classification number: H04L7/005 ,  G06F13/4265 ,  G06F2213/0026 ,  G06F2213/0042

    Abstract: This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

    Fast equalization method, chip, and communications system
    10.
    发明授权
    Fast equalization method, chip, and communications system 有权

    公开(公告)号：US11799697B2

    公开(公告)日：2023-10-24

    申请号：US17959490

    申请日：2022-10-04

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Yongyao Li ,  Fei Luo ,  Er Nie

    IPC: H04L25/03 ,  G06F13/42 ,  H04B1/38

    CPC classification number: H04L25/03012 ,  G06F13/4282 ,  H04B1/38 ,  G06F2213/0026

    Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

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