公开(公告)号：US12135597B2

公开(公告)日：2024-11-05

申请号：US16886694

申请日：2020-05-28

Applicant: Intel Corporation

Inventor： Ang Li

IPC: G06F1/32 ,  G06F1/14 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/46 ,  G06F13/38

Abstract: Systems and devices can include power management circuitry to manage the entry and exit of active state power management (APSM) link states, such as the transition between an active (L0) state and a low power state (e.g., L1). The power management circuitry can cause a downstream component to initiate an ASPM link state change negotiation based on an ASPM link state change condition being met. An ASPM event analysis logic can identify and track events that occur proximate in time to the ASPM link state change and can correlate the occurrences of the event with ASPM link state changes. An ASPM policy tuning logic can use a correlation between the occurrences of the event and ASPM link state changes to adjust or tune the ASPM link state change condition.

公开(公告)号：US20200310517A1

公开(公告)日：2020-10-01

申请号：US16886694

申请日：2020-05-28

Applicant: Intel Corporation

Inventor： Ang Li

IPC: G06F1/3206 ,  G06F1/324 ,  G06F1/14 ,  G06F13/38 ,  G06F9/46

Abstract: Systems and devices can include power management circuitry to manage the entry and exit of active state power management (APSM) link states, such as the transition between an active (L0) state and a low power state (e.g., L1). The power management circuitry can cause a downstream component to initiate an ASPM link state change negotiation based on an ASPM link state change condition being met. An ASPM event analysis logic can identify and track events that occur proximate in time to the ASPM link state change and can correlate the occurrences of the event with ASPM link state changes. An ASPM policy tuning logic can use a correlation between the occurrences of the event and ASPM link state changes to adjust or tune the ASPM link state change condition.

公开(公告)号：US20190340148A1

公开(公告)日：2019-11-07

申请号：US16513941

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

公开(公告)号：US10387304B2

公开(公告)日：2019-08-20

申请号：US15857352

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Ang Li

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1009

Abstract: Devices, systems, and methods for transferring data between the memory domain and the storage domain are described. Transferring data between domains can comprise changing the validity of the block address of the data from one domain to the other, and updating a memory domain map and a storage domain map to reflect the transfer.

公开(公告)号：US11307638B2

公开(公告)日：2022-04-19

申请号：US16217204

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Ang Li ,  Kuan Hau Tan ,  Eng Hun Ooi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F16/23 ,  G06F1/3287 ,  G06F1/3215 ,  G06F1/3206

Abstract: Methods, apparatus, and systems for securely providing multiple wake-up time options for PCI Express (PCIe) devices. Under one approach, Vendor Define Messages (VDMs) are exchanged between a host application layer in a host and a device application layer in a PCIe endpoint device coupled to the host via a PCIe link to effect changes to the L1.2 Substate exit time of a PCIe device. Under another approach, Vendor-Specific Extended Capability (VSEC) structures are exchanged between a host application layer and a device application layer to effect the changes. The VDMs and VSEC structures may also be used to enable a host to read Tpower_on capability information defining power modes supported by a PCIe device. Additionally, VSEC implementations are provided that implement VSEC components in the PCIe device transaction layer or the PCIe device application layer.

公开(公告)号：US20210357350A1

公开(公告)日：2021-11-18

申请号：US17387261

申请日：2021-07-28

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

公开(公告)号：US20190114281A1

公开(公告)日：2019-04-18

申请号：US16219922

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Ang Li ,  Kuan Hua Tan

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and device can involve an application layer logic implemented at least partially in hardware circuitry; a first port for transmitting information across a multi-lane link, the first port comprising a protocol stack; a memory element, the memory element comprising mapping between an event identifier value and an event identifier carrier value, the event identifier identifying an event to be carried out by the application layer logic across the multi-lane link, the event identifier carrier value mapped to the event identifier, the application layer logic to transmit the event identifier carrier value across the link prior to executing the event.

公开(公告)号：US11704275B2

公开(公告)日：2023-07-18

申请号：US17387261

申请日：2021-07-28

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

CPC classification number: G06F13/4221 ,  G06F9/44505 ,  G06F2213/0026

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

公开(公告)号：US20190220422A1

公开(公告)日：2019-07-18

申请号：US16367846

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Ang Li ,  Eng Hun Ooi

IPC: G06F13/16 ,  G06F1/3234 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/50

CPC classification number: G06F13/161 ,  G06F1/3206 ,  G06F1/3253 ,  G06F9/30101 ,  G06F9/5005 ,  G06F2213/0026

Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.

公开(公告)号：US20190042155A1

公开(公告)日：2019-02-07

申请号：US15978766

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Ang Li ,  Sahar Khalili ,  Su Wei Lim ,  Robert Royer, JR.

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06

Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.