公开(公告)号：US10950784B2

公开(公告)日：2021-03-16

申请号：US16434414

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Chu-Jie Huang

IPC: H01L29/04 ,  H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and has a lattice constant less than that of the active metal layer.

公开(公告)号：US20200343265A1

公开(公告)日：2020-10-29

申请号：US16394207

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L27/11585 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

公开(公告)号：US20200295085A1

公开(公告)日：2020-09-17

申请号：US16887232

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L27/11507 ,  H01L45/00 ,  H01L43/12 ,  H01L27/22

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.

公开(公告)号：US10727337B2

公开(公告)日：2020-07-28

申请号：US16207081

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi Tu ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tong-Chern Ong ,  Wen-Ting Chu

IPC: H01L29/78 ,  H01L29/51 ,  G11C11/22 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/66

Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

公开(公告)号：US10727275B2

公开(公告)日：2020-07-28

申请号：US16156026

申请日：2018-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu

IPC: H01L27/24 ,  H01L23/528 ,  H01L23/522 ,  H01L45/00 ,  H01L21/768

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

公开(公告)号：US20200027924A1

公开(公告)日：2020-01-23

申请号：US16587693

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chieh Yang ,  Chih-Yang Chang ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.

公开(公告)号：US10311952B2

公开(公告)日：2019-06-04

申请号：US15937257

申请日：2018-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chieh Yang ,  Chih-Yang Chang ,  Chang-Sheng Liao ,  Hsia-Wei Chen ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Manish Kumar Singh ,  Chi-Tsai Chen

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.

公开(公告)号：US10249756B2

公开(公告)日：2019-04-02

申请号：US15640127

申请日：2017-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi Tu ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tong-Chern Ong ,  Wen-Ting Chu

IPC: H01L29/78 ,  G11C11/22 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

公开(公告)号：US20180375022A1

公开(公告)日：2018-12-27

申请号：US15633101

申请日：2017-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin ,  Wen-Ting Chu

IPC: H01L45/00

Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.

公开(公告)号：US20180374901A1

公开(公告)日：2018-12-27

申请号：US16108594

申请日：2018-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.