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    INTEGRATED CIRCUIT DEVICES INCLUDING CONTACTS AND METHODS OF FORMING THE SAME
    41.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING CONTACTS AND METHODS OF FORMING THE SAME 有权
    包括联系人的集成电路设备及其形成方法

    公开(公告)号：US20150243747A1

    公开(公告)日：2015-08-27

    申请号：US14628541

    申请日：2015-02-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Dharmendar Reddy Palle ,  Mark S. Rodder

    IPC: H01L29/417 ,  H01L29/45 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion.

    Abstract translation: 提供了包括触点的集成电路装置及其形成方法。 器件可以包括衬底上的翅片，翅片上的栅极结构和栅极结构侧的鳍中的源极/漏极区域。 所述装置还可以包括覆盖源极/漏极区域的最上表面和栅极结构的侧壁的接触插塞。 接触插塞可以包括包括第一材料的内部部分和包括不同于第一材料的第二材料的外部部分。 外部部分可以至少部分地覆盖内部部分的侧壁，并且外部部分的一部分可以设置在门结构的侧壁和内部部分的侧壁之间。

    INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND METHODS OF FORMING THE SAME
    42.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND METHODS OF FORMING THE SAME 有权
    包含应变通道区域的集成电路装置及其形成方法

    公开(公告)号：US20150123075A1

    公开(公告)日：2015-05-07

    申请号：US14304008

    申请日：2014-06-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ryan M. Hatcher ,  Mark S. Rodder ,  Robert C. Bowen ,  Jorge A. Kittl

    IPC: H01L29/10 ,  H01L29/15 ,  H01L29/78

    CPC classification number: H01L29/7781 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/122 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66431 ,  H01L29/785

    Abstract: Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness TW sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

    Abstract translation: 提供包括应变通道区域的集成电路器件及其形成方法。 集成电路器件可以包括增强型场效应晶体管。 增强型场效应晶体管可以包括具有足够的阱厚度TW的量子阱沟道区，其足以产生其中的多个等效电子传导状态的应变引起的分裂到相应的不等能级，包括与 当表面被偏置到反转状态时，邻近通道区域的表面的最低表面粗糙度散射。

    METHODS OF FORMING FIELD EFFECT TRANSISTORS, INCLUDING FORMING SOURCE AND DRAIN REGIONS IN RECESSES OF SEMICONDUCTOR FINS
    43.
    发明申请
    METHODS OF FORMING FIELD EFFECT TRANSISTORS, INCLUDING FORMING SOURCE AND DRAIN REGIONS IN RECESSES OF SEMICONDUCTOR FINS 有权
    形成场效应晶体的方法，包括形成半导体寄存器的形成源和漏区

    公开(公告)号：US20140322882A1

    公开(公告)日：2014-10-30

    申请号：US13870471

    申请日：2013-04-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mark S. Rodder ,  Dong-Won Kim

    IPC: H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7856

    Abstract: Methods of forming a fin-shaped Field Effect Transistor (FinFET) are provided. The methods may include selectively incorporating source/drain extension-region dopants into source and drain regions of a semiconductor fin, using a mask to block incorporation of the source/drain extension-region dopants into at least portions of the semiconductor fin. The methods may include removing portions of the source and drain regions of the semiconductor fin to define recesses therein. The methods may include epitaxially growing source and drain regions from the recesses in the semiconductor fin.

    Abstract translation: 提供了形成鳍状场效应晶体管（FinFET）的方法。 所述方法可以包括使用掩模来将源极/漏极延伸区掺杂物选择性地并入到半导体鳍片的源极和漏极区域中，以阻止源极/漏极延伸区掺杂物掺入到半导体鳍片的至少部分中。 所述方法可以包括去除半导体鳍片的源区和漏区的部分以在其中限定凹陷。 所述方法可以包括从半导体鳍片中的凹部外延生长源极和漏极区域。

    METHODS OF FABRICATING NON-PLANAR TRANSISTORS INCLUDING CURRENT ENHANCING STRUCTURES
    44.
    发明申请
    METHODS OF FABRICATING NON-PLANAR TRANSISTORS INCLUDING CURRENT ENHANCING STRUCTURES 有权
    制造非平面晶体管的方法，包括电流增强结构

    公开(公告)号：US20140273397A1

    公开(公告)日：2014-09-18

    申请号：US13801001

    申请日：2013-03-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mark S. Rodder ,  Kang-ill Seo

    IPC: H01L21/76

    CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/7848

    Abstract: Methods of fabricating non-planar transistors including current enhancing structures are provided. The methods may include forming first and second fin structures directly adjacent each other overlying a substrate including an isolation layer. The methods may further include forming a spacer on the isolation layer including first and second recesses exposing upper surfaces of the first and second fin structures respectively. The spacer may cover an upper surface of the isolation layer between the first and second recesses. The methods may also include forming first and second current enhancing structures contacting the first and second fin structures, respectively, in the first and second recesses.

    Abstract translation: 提供了制造包括电流增强结构的非平面晶体管的方法。 所述方法可以包括形成直接相邻的第一和第二翅片结构，覆盖包括隔离层的基底。 所述方法还可以包括在隔离层上形成间隔物，其包括分别暴露第一和第二翅片结构的上表面的第一和第二凹部。 间隔件可以覆盖第一和第二凹部之间的隔离层的上表面。 所述方法还可以包括分别在第一和第二凹部中形成接触第一和第二鳍片结构的第一和第二电流增强结构。

    Methods of fabricating integrated circuit device with fin transistors having different threshold voltages
    45.
    发明授权
    Methods of fabricating integrated circuit device with fin transistors having different threshold voltages 有权
    制造具有不同阈值电压的鳍式晶体管的集成电路器件的方法

    公开(公告)号：US08828818B1

    公开(公告)日：2014-09-09

    申请号：US13801367

    申请日：2013-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mark S. Rodder

    IPC: H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L21/845

    Abstract: Methods of fabricating integrated circuit device with fin transistors having different threshold voltages are provided. The methods may include forming first and second semiconductor fins including first and second semiconductor materials, respectively, and covering at least one among the first and second semiconductor fins with a mask. The methods may further include depositing a compound semiconductor layer including the first and second semiconductor materials directly onto sidewalls of the first and second semiconductor fins not covered by the mask and oxidizing the compound semiconductor layer. The oxidization process oxidizes the first semiconductor material within the compound semiconductor layer while driving the second semiconductor material within the compound semiconductor layer into the sidewalls of the first and second semiconductor fins not covered by the mask.

    Abstract translation: 提供了制造具有不同阈值电压的鳍式晶体管的集成电路器件的方法。 所述方法可以包括分别形成包括第一和第二半导体材料的第一和第二半导体鳍片，并用掩模覆盖第一和第二半导体鳍片中的至少一个。 所述方法还可以包括将包括第一和第二半导体材料的化合物半导体层直接沉积在未被掩模覆盖的第一和第二半导体鳍片的侧壁上，并氧化化合物半导体层。 氧化过程将化合物半导体层内的第一半导体材料氧化，同时将化合物半导体层内的第二半导体材料驱动到未被掩模覆盖的第一和第二半导体鳍片的侧壁中。

    Semiconductor device and method for making the same
    49.
    发明授权
    Semiconductor device and method for making the same 有权

    公开(公告)号：US10811415B2

    公开(公告)日：2020-10-20

    申请号：US16298887

    申请日：2019-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Vassilios Gerousis ,  Mark S. Rodder

    IPC: H01L27/092 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

    Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

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