公开(公告)号：US20180294226A1

公开(公告)日：2018-10-11

申请号：US15946075

申请日：2018-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Boong Lee ,  Jung-Ho Do ,  Tae-Joong Song ,  Seung-Young Lee ,  Jong-Hoon Jung ,  Ji-Su Yu

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L21/8234

Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

公开(公告)号：US10037401B2

公开(公告)日：2018-07-31

申请号：US15896415

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Sanghoon Baek ,  Sungwe Cho ,  Jung-Ho Do ,  Giyoung Yang ,  Jinyoung Lim

IPC: G06F17/50 ,  H01L27/118 ,  H01L27/02

CPC classification number: G06F17/5077 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

公开(公告)号：US10026688B2

公开(公告)日：2018-07-17

申请号：US15692670

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoung Lee ,  Sanghoon Baek ,  Jung-Ho Do

IPC: H01L21/4763 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

公开(公告)号：US09929023B2

公开(公告)日：2018-03-27

申请号：US15350716

申请日：2016-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Jonghoon Jung ,  Sanghoon Baek ,  Seungyoung Lee ,  Taejoong Song ,  Jinyoung Lim

IPC: H01L21/8238 ,  H01L21/3213

CPC classification number: H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.

公开(公告)号：US09887210B2

公开(公告)日：2018-02-06

申请号：US15238912

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

IPC: H01L21/76 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/8238 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20160351583A1

公开(公告)日：2016-12-01

申请号：US15232223

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon BAEK ,  Sang-kyu Oh ,  Jung-Ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

Abstract translation: 集成电路（IC）可以包括至少一个单元，其包括在垂直于第一方向的第二方向上在第一方向上延伸并彼此平行的多条导线，第一触点分别设置在两侧 的至少一条导线，以及设置在所述至少一个导电线上的第二触点，并且所述第一触点通过电连接到所述至少一个导线和所述第一触点而形成单个节点 。

公开(公告)号：US09496179B2

公开(公告)日：2016-11-15

申请号：US14833922

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sunyoung Park ,  Sang-Kyu Oh ,  Jintae Kim ,  Hyosig Won

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/321

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/41758 ,  H01L29/66568

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

Abstract translation: 一种制造半导体器件的方法包括：在基板上形成与有源图案交叉的有源图案和栅电极，在栅电极侧形成连接到有源图案的第一触点，形成连接到栅电极的第二触点 并且形成在栅电极侧与第一接触连接的第三触点。 使用不同于用于形成第一接触的光掩模形成第三接触。 第三触点的底表面设置在低于第一触点的顶表面的高度的装置中的水平面上。

公开(公告)号：US20140162460A1

公开(公告)日：2014-06-12

申请号：US13950799

申请日：2013-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-JONG LEE ,  Soo-Han Choi ,  Jung-Ho Do ,  Chul-Hong Park ,  Sang-Pil Sim

IPC: G06F17/50 ,  H01L21/308

CPC classification number: G06F17/5081 ,  H01L21/3086

Abstract: A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Abstract translation: 形成图案的方法包括限定多个图案，限定接触所述多个图案并对应于所述图案之间的区域的多个倾斜违规图案，将所述多个音高违规图案分类为第一区域和第二区域， 与第一区域相邻，选择第一区域和第二区域中的一个，以及形成被定义为所选择的第一或第二区域的初始图案。 所述选择包括执行以下各项中的至少一个：i）选择接触虚拟图案的区域，ii）选择与一个区域相同类型的区域，以及iii）从所述第一区域选择与外壳的凹部接触的区域，以及 第二个地区。