公开(公告)号：US09773708B1

公开(公告)日：2017-09-26

申请号：US15245634

申请日：2016-08-24

申请人： GLOBALFOUNDRIES Inc.

发明人： John Zhang ,  Steven Bentley ,  Kwan-Yong Lim

IPC分类号： H01L21/8238 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L27/092

CPC分类号： H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： Devices and methods of fabricating vertical field effect transistors on semiconductor devices are provided. One intermediate semiconductor includes: a substrate, a bottom spacer layer above the substrate, a plurality of fins, wherein at least one fin is an n-fin and at least one fin is a p-fin; a high-k layer and a work function metal over the bottom spacer layer and around the plurality of fins; a top spacer above the high-k layer and the work function metal and surrounding a top area of the fins; a top source/drain structure over each fin; a dielectric capping layer over the top source/drain structure; a fill metal surrounding the work function metal; and a liner.

公开(公告)号：US09761662B1

公开(公告)日：2017-09-12

申请号：US15423647

申请日：2017-02-03

申请人： GLOBALFOUNDRIES INC.

发明人： Bipul C. Paul ,  Kwan-Yong Lim

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/786 ,  H01L29/423

CPC分类号： H01L27/1108 ,  H01L21/823814 ,  H01L21/823885

摘要： Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.

公开(公告)号：US20160268257A1

公开(公告)日：2016-09-15

申请号：US14656412

申请日：2015-03-12

申请人： GLOBALFOUNDRIES Inc.

发明人： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC分类号： H01L27/088 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/41791 ,  G06F17/5072 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

摘要： At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

摘要翻译： 本文公开的至少一种方法，装置和系统，用于抑制在鳍状场效应晶体管（finFET）的鳍片上形成的外延层的过度生长，以防止单独finFET器件的鳍片之间的短路。 形成第一晶体管的一组翅片。 翅片组包括第一外翅片，内翅片和第二外翅片。 执行氧化物沉积工艺以在该组翅片上沉积氧化物材料。 执行第一凹陷处理以去除一部分氧化物材料。 这使得留在第一和第二外鳍的内壁上的氧化物材料的一部分留下。 进行间隔氮化物沉积工艺。 执行间隔氮化物去除工艺，在第一和第二外部散热片的外壁处留下间隔氮化物材料。 执行第二凹陷处理以从第一和第二外鳍的内壁去除氧化物材料。 在该组翅片上进行外延层沉积。 在第一和第二外部翅片的外壁上的外延层的横向过度生长的一部分被间隔氮化物材料抑制。

公开(公告)号：US20150318288A1

公开(公告)日：2015-11-05

申请号：US14267405

申请日：2014-05-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim

IPC分类号： H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/1104 ,  H01L29/66666 ,  H01L29/7827

摘要： Various methods of forming a vertical static random access memory cell and the resulting devices are disclosed. One method includes forming a plurality of pillars of semiconductor material on a substrate, forming first source/drain regions on a lower portion of each of the pillars, forming a gate electrode around each of the pillars above the first source/drain region, forming a second source/drain region on a top portion of each of the pillars above the gate electrode, wherein the first and second source/drain regions and the gate electrode on each pillar defines a vertical transistor, and interconnecting the vertical transistors to define a static random access memory cell.

摘要翻译： 公开了形成垂直静态随机存取存储器单元和所得到的器件的各种方法。 一种方法包括在衬底上形成多个半导体材料柱，在每个柱的下部形成第一源极/漏极区，在第一源极/漏极区之上的每个柱上形成栅电极，形成栅电极 在栅电极上方的每个柱的顶部上的第二源极/漏极区，其中每个柱上的第一和第二源极/漏极区域和栅极电极限定垂直晶体管，并且互连垂直晶体管以限定静态随机 访问存储单元

公开(公告)号：US10121868B1

公开(公告)日：2018-11-06

申请号：US15585865

申请日：2017-05-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material.

公开(公告)号：US20180226402A1

公开(公告)日：2018-08-09

申请号：US15427403

申请日：2017-02-08

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Min Gyu Sung ,  Kwan-Yong Lim

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311

CPC分类号： H01L27/0886 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/7827

摘要： Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

公开(公告)号：US09847418B1

公开(公告)日：2017-12-19

申请号：US15219917

申请日：2016-07-26

申请人： GLOBALFOUNDRIES Inc.

发明人： Kwan-Yong Lim ,  Min Gyu Sung ,  Chanro Park

IPC分类号： H01L21/33 ,  H01L21/20 ,  H01L21/36 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

摘要： A method includes forming a fin on a substrate. A first liner is formed on the fin. A first dielectric layer is formed above the first liner. A patterned hard mask is formed above the first dielectric layer and has a fin cut opening defined therein. Portions of the first dielectric layer and the first liner disposed below the fin cut opening are removed to expose a portion of the fin. The patterned hard mask layer is removed. The exposed portion of the fin is oxidized to define a diffusion break in the fin.

公开(公告)号：US09711511B1

公开(公告)日：2017-07-18

申请号：US15193867

申请日：2016-06-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim ,  Motoi Ichihashi ,  Youngtag Woo ,  Deepak Nayak

IPC分类号： H01L29/66 ,  H01L27/11 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417

CPC分类号： H01L27/1104 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/7827

摘要： A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

公开(公告)号：US20170200797A1

公开(公告)日：2017-07-13

申请号：US15472924

申请日：2017-03-29

申请人： GLOBALFOUNDRIES INC.

发明人： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC分类号： H01L29/417 ,  H01L29/06 ,  G06F17/50 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/41791 ,  G06F17/5072 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

摘要： At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

公开(公告)号：US09640533B2

公开(公告)日：2017-05-02

申请号：US14656412

申请日：2015-03-12

申请人： GLOBALFOUNDRIES Inc.

发明人： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/165

CPC分类号： H01L29/41791 ,  G06F17/5072 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

摘要： At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.