公开(公告)号：US20100277978A1

公开(公告)日：2010-11-04

申请号：US12768055

申请日：2010-04-27

Applicant: Ji-Ho CHO

Inventor： Ji-Ho CHO

IPC: G11C16/02 ,  G11C16/28

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C2211/5634

Abstract: Provided is a flash memory device. The flash memory device includes: a memory cell storing multi-bit data; a reference bias voltage supply circuit generating a reference bias voltage; an sense amplifier sensing the multi-bit data stored in the memory cell using the reference bias voltage; and a control circuit controlling the reference bias voltage supply circuit. The control circuit controls the reference bias voltage supply circuit to allow the reference bias voltage to be developed according to a change of a main word line voltage applied to the memory cell during a read operation.

Abstract translation: 提供了一种闪存设备。 闪速存储器件包括：存储多位数据的存储单元; 产生参考偏置电压的参考偏置电压电路; 感测放大器，使用参考偏置电压感测存储在存储单元中的多位数据; 以及控制基准偏置电压供给电路的控制电路。 控制电路控制参考偏置电压供应电路，以允许根据在读取操作期间施加到存储器单元的主字线电压的变化来显影参考偏置电压。

公开(公告)号：US20100271881A1

公开(公告)日：2010-10-28

申请号：US12754149

申请日：2010-04-05

Applicant: Eiichi MAKINO

Inventor： Eiichi MAKINO

IPC: G11C16/02 ,  G11C5/14 ,  G11C8/00 ,  G11C11/00

CPC classification number: G11C16/30 ,  G11C5/145

Abstract: A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit.

Abstract translation: 一种半导体集成电路装置，具备包括多个存储单元的多个平面的存储单元阵列，电源电压生成电路，具备：电压生成电路，其被配置为生成上述多个面共有的电源电压;选择部 数字检测电路，被配置为检测所述多个平面中的选定平面的数量;以及电阻可变电路，被配置为根据所选择的平面的数量来改变所述多个平面与所述电压产生电路之间的布线电阻 以及被配置为控制电源电压产生电路的控制电路。

公开(公告)号：US20100265764A1

公开(公告)日：2010-10-21

申请号：US12662103

申请日：2010-03-31

Applicant: Han Woong Yoo ,  Jaehong Kim ,  Junjin Kong

Inventor： Han Woong Yoo ,  Jaehong Kim ,  Junjin Kong

IPC: G11C16/02

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5648

Abstract: Methods of accessing storage devices. The methods include rearranging a writing order of continuous first and second data according to a reading order, and writing the first and second data in a first and second storage region of the storage device, respectively, according to the writing order. The reading order reads the second storage region first that provides interference on the first storage region.

Abstract translation: 访问存储设备的方法 这些方法包括根据读取顺序重新排列连续的第一和第二数据的写入顺序，以及根据写入顺序将第一和第二数据分别写入存储装置的第一和第二存储区域。 读取顺序首先读取在第一存储区域上提供干扰的第二存储区域。

公开(公告)号：US20100195397A1

公开(公告)日：2010-08-05

申请号：US12757833

申请日：2010-04-09

Applicant: Gerrit Jan Hemink

Inventor： Gerrit Jan Hemink

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3404

Abstract: A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The level of boosting in the channel region of the inhibited NAND string is governed by the pre-charge voltage and the soft programming voltage. By controlling the pre-charge voltage, more reliable and consistent channel boosting can be achieved. In one embodiment, the pre-charge voltage is increased between applications of the soft programming voltage to reduce or eliminate a rise in the channel's boosted potential. In one embodiment, the soft programming pre-charge voltage level(s) is determined during testing that is performed as part of a manufacturing process.

Abstract translation: 软编程预充电电压在非易失性存储器件的软编程操作期间提供升压控制。 可以将预充电电压施加到一块存储器单元的字线，以使得能够预先对NAND串的通道区进行预编程以禁止软编程。 被禁止的NAND串的通道区域中的升压电平由预充电电压和软编程电压控制。 通过控制预充电电压，可以实现更可靠和一致的通道增压。 在一个实施例中，在应用软编程电压之间增加预充电电压以减少或消除通道的升压电位的上升。 在一个实施例中，软编程预充电电压电平在作为制造过程的一部分执行的测试期间被确定。

公开(公告)号：US20100195396A1

公开(公告)日：2010-08-05

申请号：US12698576

申请日：2010-02-02

Applicant: Tsutomu HIGUCHI

Inventor： Tsutomu HIGUCHI

IPC: G11C16/02 ,  G11C29/00 ,  G11C7/10

CPC classification number: G11C29/48 ,  G06F11/1068 ,  G11C11/41 ,  G11C16/04 ,  G11C29/02 ,  G11C29/1201 ,  G11C29/14 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2029/3202

Abstract: A semiconductor memory device includes a main memory includes a nonvolatile memory, and a buffer which stores input/output data of the nonvolatile memory, a buffer unit of the main memory, the buffer unit includes a volatile memory, a self-test interface includes a data input/output pin, and a controller which controls the main memory and the buffer unit. The controller at least stores data in the buffer from the self-test interface via the data input/output pin.

Abstract translation: 半导体存储器件包括：主存储器，包括非易失性存储器和存储非易失性存储器的输入/输出数据的缓冲器，主存储器的缓冲单元，缓冲器单元包括易失性存储器，自检接口包括： 数据输入/输出引脚，以及控制主存储器和缓冲单元的控制器。 控制器至少通过数据输入/输出引脚将数据存储在自检接口的缓冲器中。

公开(公告)号：US20100103734A1

公开(公告)日：2010-04-29

申请号：US12427013

申请日：2009-04-21

Applicant: Gerrit Jan Hemink

Inventor： Gerrit Jan Hemink

IPC: G11C16/02 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3468 ,  G11C16/3486 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results.

Abstract translation: 对多个非易失性存储元件执行多个编程处理。 编程过程中的每一个都使用编程脉冲来操作至少一个非易失性存储元件的子集到相应的目标条件集合。 编程过程的至少一个子集包括识别与实现相应编程处理的特定结果相关联的编程脉冲，并且以非易失性存储元件的一个或多个替代结果执行一个或多个感测操作。 如果一个或多个感测操作确定大于预定数量的非易失性存储元件实现了第一替代结果，则基于第一替代结果和编程脉冲的识别来调整后续编程处理。 如果一个或多个感测操作确定小于所需数量的非易失性存储元件实现任何替代结果，则基于编程脉冲的识别来调整后续编程处理。

公开(公告)号：US07679952B2

公开(公告)日：2010-03-16

申请号：US12096226

申请日：2006-12-04

Applicant: Nicolaas Lambert ,  Victor Martinus Gerardus Van Acht ,  Pierre Hermanus Woerlee ,  Andrei Mijiritskii

Inventor： Nicolaas Lambert ,  Victor Martinus Gerardus Van Acht ,  Pierre Hermanus Woerlee ,  Andrei Mijiritskii

IPC: G11C16/02 ,  H01L27/105

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C17/16 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2454 ,  H01L27/2472

Abstract: In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.

Abstract translation: 在示例实施例中，电子电路包括具有存储器单元的行和列的存储器矩阵。 为每行提供第一行导体。 第二行导体对应于行对，每个连续的行与前面的行之一形成相应的对，使得每一对与下一对的一行重叠。 为每个列提供列导体。 每个存储单元包括存取晶体管，节点和第一和第二电阻存储器元件。 存取晶体管具有耦合到存储单元行的第一行导体的控制电极，耦合在存储单元的列的列导体和节点之间的主电流通道。 第一和第二电阻性存储器元件耦合在该存储器单元所属的行对之间的节点和第二行导体之间。

公开(公告)号：US20100002511A1

公开(公告)日：2010-01-07

申请号：US12443528

申请日：2007-09-27

Applicant: Guoqiao Tao ,  Steven V. E. S. Van Dijk

Inventor： Guoqiao Tao ,  Steven V. E. S. Van Dijk

IPC: G11C16/22 ,  G11C16/02

CPC classification number: G11C16/22

Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1′, D1″) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.

Abstract translation: 本发明涉及一种非易失性存储器件，包括：用于提供要存储在非易失性存储器件上的外部数据（D1）的输入; 和第一非易失性存储器块（100）和第二非易失性存储器块（200），所述第一非易失性存储器块（100）和所述第二非易失性存储器块（200）设置在单个管芯 （10），其中第一非易失性存储器块（100）和第二非易失性存储器块（200）是不同类型的，使得第一非易失性存储器块（100）和第二非易失性存储器块 （200）需要不兼容的外部攻击技术以便从其中检索数据，外部数据（D1）以分布式方式（D1'，D1“）存储到第一非易失性存储器块（100）和 第二非易失性存储器块（200）。 本发明还涉及在非易失性存储器件中保护数据的方法。

公开(公告)号：US20090296466A1

公开(公告)日：2009-12-03

申请号：US12385705

申请日：2009-04-16

Applicant: Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

Inventor： Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

IPC: G11C16/02 ,  G11C16/06

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621

Abstract: Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.

Abstract translation: 提供的是存储器件和存储器编程方法。 存储器设备可以包括：包括多个存储器单元的多位单元阵列; 提取每个存储单元的状态信息的控制器，将多个存储单元划分为第一组和第二组，将第一验证电压分配给第一组的存储单元，并将第二验证电压分配给存储单元 第二组 以及编程单元，其改变第一组的每个存储单元的阈值电压，直到第一组的每个存储单元的阈值电压大于或等于第一验证电压，并且改变每个存储单元的阈值电压 直到第二组的每个存储单元的阈值电压大于或等于第二验证电压。

公开(公告)号：US20090187798A1

公开(公告)日：2009-07-23

申请号：US12042551

申请日：2008-03-05

Applicant: Jin-Ki KIM

Inventor： Jin-Ki KIM

IPC: G11C29/00 ,  G06F11/07 ,  G11C16/02 ,  G11C5/02

CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C29/76 ,  H04L12/46

Abstract: A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.

Abstract translation: 公开了具有两个存储容量的非功率的非易失性存储器。 非易失性存储器件包括至少一个平面。 平面包括多个块，其中每个块划分成多个页面，并且每个块沿着第一维由第一数量的存储单元定义用于存储数据，并且沿着第二维度由第二数量的第二维度 用于存储数据的存储单元。 非易失性存储器具有与所述平面中的存储单元的总数成比例地相关的两个容量的非功率。 非易失性存储器还包括多个行解码器。 在存储器装置中，至少基本上一对一的关系存在多个行解码器到页数。 行解码器中的每一个被配置为便于在存储器件的相关页面上进行读取操作。