公开(公告)号：US20060097820A1

公开(公告)日：2006-05-11

申请号：US11267754

申请日：2005-11-03

Applicant: Shoji Watanabe ,  Tsutomu Higuchi

Inventor： Shoji Watanabe ,  Tsutomu Higuchi

IPC: H01P5/10

CPC classification number: H05K1/165 ,  H01P5/10 ,  H05K3/0023 ,  H05K3/184 ,  H05K2201/09318

Abstract: A printed circuit board built-in type planar balun which can be easily incorporated in a printed circuit board without increasing the number of layers and lowering the functions thereof is provided. A balanced signal transmission line 1 and an unbalanced signal transmission line 2 are formed on a same plane, with the sides being opposed to each other. Dielectric layers 3 are provided between these transmission lines, and between the transmission line and a ground potential layer 4 which is arranged substantially parallel to the lines 1 and 2 and spaced at a predetermined distance.

Abstract translation: 提供了一种内置式平面平衡 - 不平衡变换器的印刷电路板，其可以容易地结合在印刷电路板中而不增加层数并降低其功能。 平衡信号传输线1和不平衡信号传输线2形成在同一平面上，并且侧面彼此相对。 电介质层3设置在这些传输线之间，传输线和接地电位层4之间，该接地电位层4基本上平行于线路1和2布置并以预定距离隔开。

公开(公告)号：US06552694B1

公开(公告)日：2003-04-22

申请号：US09609974

申请日：2000-07-06

Applicant: Tomoharu Fujii ,  Shigeru Okamura ,  Tsutomu Higuchi ,  Masatoshi Akagawa

Inventor： Tomoharu Fujii ,  Shigeru Okamura ,  Tsutomu Higuchi ,  Masatoshi Akagawa

IPC: H01Q1112

CPC classification number: H01Q1/2225 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  G06K19/07783 ,  G06K19/07784 ,  H01L2924/0002 ,  H01Q1/22 ,  H01Q7/00 ,  H01L2924/00

Abstract: A semiconductor device with an antenna including one or more antenna units for sending and receiving signals and a semiconductor element electrically connected to the antenna units, wherein the antenna units are formed by pressing or etching a thin metal sheet with substantially the same flat surface size as the semiconductor element, and the antenna units are integrally coupled to the surface of the semicondcutor element. The antenna units are formed in a plurality of layers separated by insulating layers, and the antenna units formed on the respective layers are connected electrically in series with each other.

Abstract translation: 一种具有天线的半导体器件，包括用于发送和接收信号的一个或多个天线单元和与天线单元电连接的半导体元件，其中天线单元通过压制或蚀刻具有基本相同的平坦表面尺寸的薄金属片而形成， 半导体元件和天线单元一体地耦合到半切割元件的表面。 天线单元形成为由绝缘层分隔开的多个层，并且形成在各层上的天线单元彼此串联连接。

公开(公告)号：US06501440B2

公开(公告)日：2002-12-31

申请号：US09946238

申请日：2001-09-05

Applicant: Yoshitaka Matsushita ,  Tsutomu Higuchi

Inventor： Yoshitaka Matsushita ,  Tsutomu Higuchi

IPC: H01Q322

CPC classification number: G06K19/0775 ,  G06K19/02 ,  G06K19/07749 ,  G06K19/07779 ,  G06K19/07781

Abstract: An IC card includes an antenna formed as a flat coil wound several times having an inner vacant area, said antenna being made by punching or etching a thin metal strip and having an outermost loop partially connected to and supported by an outer frame of said thin metal strip, and said antenna having respective innermost and outermost terminals. A semiconductor element is electrically connected to said innermost and outermost terminals, respectively. One of said innermost and outermost terminals having an accommodation hole in which said semiconductor element is accommodated. The semiconductor element and the antenna are supported to maintain their form by a supporting material made of biodegradable resin.

公开(公告)号：US07525845B2

公开(公告)日：2009-04-28

申请号：US11785527

申请日：2007-04-18

Applicant: Hirokazu Miyazaki ,  Katsuaki Matsui ,  Tsutomu Higuchi

Inventor： Hirokazu Miyazaki ,  Katsuaki Matsui ,  Tsutomu Higuchi

IPC: G11C11/34

CPC classification number: G11C7/067 ,  G11C7/08 ,  G11C16/0441 ,  G11C16/26

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract translation: 在由闪速存储器构成的存储单元阵列中，多个提供了一对具有相互相反值的数据被写入的正存储单元和负存储单元。 连接到数据读取对象的存储单元的位线和I / O线被充电，然后提高连接到数据读取对象存储单元的字线的电位WL。 因此，根据写入的数据，电流在数据读取对象存储单元中流动，因此I / O线的电位BL和电位BLN之一开始下降。 当电位BL和BLN中的一个低于读出放大器的电路阈值时，建立读取数据，并将所建立的读取数据作为读出放大器输出信号SAOUT输出。

公开(公告)号：US20050169032A1

公开(公告)日：2005-08-04

申请号：US11094236

申请日：2005-03-31

Applicant: Tsutomu Higuchi

Inventor： Tsutomu Higuchi

IPC: G11C11/407 ,  G11C5/02 ,  G11C11/401 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10897 ,  G11C5/025

Abstract: A memory macro includes a variable number of memory cell arrays and associated circuits, and peripheral circuit elements such as line drivers, power-source transistors, and power-source capacitors coupled to the associated circuits. Multiple peripheral circuit elements of one type are placed side by side in a certain direction, aligned in that direction with one or more memory cell arrays, and are coupled in parallel to the associated circuits of those memory cell arrays. The number of these peripheral circuit elements is selected according to the number of memory cell arrays aligned with them, so that electrical requirements can be met without unnecessary consumption of space or current.

Abstract translation: 存储器宏包括可变数量的存储单元阵列和相关电路，以及外围电路元件，例如线路驱动器，功率源晶体管和耦合到相关电路的功率源电容器。 一种类型的多个外围电路元件在一定方向并排放置，在该方向上与一个或多个存储单元阵列对准，并且并联耦合到那些存储单元阵列的相关电路。 这些外围电路元件的数量根据与它们对准的存储单元阵列的数量来选择，使得可以满足电气要求而不需要空间或电流的消耗。

公开(公告)号：US06544664B1

公开(公告)日：2003-04-08

申请号：US09577958

申请日：2000-05-24

Applicant: Naotomi Takahashi ,  Yoichi Babasaki ,  Tsutomu Higuchi ,  Osamu Nakano ,  Hiroshi Watanabe ,  Masaru Takahashi ,  Makoto Dobashi

Inventor： Naotomi Takahashi ,  Yoichi Babasaki ,  Tsutomu Higuchi ,  Osamu Nakano ,  Hiroshi Watanabe ,  Masaru Takahashi ,  Makoto Dobashi

IPC: B32B1500

CPC classification number: H05K3/388 ,  C23C14/16 ,  Y10T428/12438 ,  Y10T428/12847 ,  Y10T428/12903 ,  Y10T428/265

Abstract: A copper foil for use in making a printed wiring board and a copper clad laminate comprising the copper foil are herein disclosed and the copper foil is characterized in that a metal chromium layer is formed on at least one side of the copper foil by vapor deposition or characterized in that one side of the copper foil is supported by a carrier through a releasing layer and a metal chromium layer is formed on the other side of the foil by vapor deposition. The copper foil is excellent in the adhesion to various substrates (the peel strength between the substrate and the copper foil), moisture resistance, chemical resistance and heat resistance and therefore, the copper foil can suitably be used in the production of printed wiring boards.

Abstract translation: 本文公开了一种用于制造印刷电路板的铜箔和包含铜箔的覆铜层压板，铜箔的特征在于，通过气相沉积在铜箔的至少一侧上形成金属铬层， 其特征在于，铜箔的一面由载体通过脱模层支撑，并且通过气相沉积在箔的另一侧上形成金属铬层。 铜箔对各种基板的粘附性（基板和铜箔之间的剥离强度），耐湿性，耐化学性和耐热性优异，因此铜箔可以适用于印刷电路板的制造。

公开(公告)号：US06541126B1

公开(公告)日：2003-04-01

申请号：US09830122

申请日：2001-04-23

Applicant: Junshi Yoshioka ,  Akiko Sugimoto ,  Sakiko Taenaka ,  Makoto Dobashi ,  Tsutomu Higuchi ,  Takuya Yamamoto ,  Ken-ichiro Iwakiri

Inventor： Junshi Yoshioka ,  Akiko Sugimoto ,  Sakiko Taenaka ,  Makoto Dobashi ,  Tsutomu Higuchi ,  Takuya Yamamoto ,  Ken-ichiro Iwakiri

IPC: B32B1504

CPC classification number: H05K3/025 ,  C25D1/04 ,  C25D1/22 ,  Y10T428/12556 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/24851 ,  Y10T428/2495 ,  Y10T428/31678

Abstract: To provide an electrodeposited copper foil with carrier, in which electrical connection holes such as through holes (PTH), interstitial via holes (IVH), and blind via holes (BVH) can be readily formed. The invention provides an electrodeposited copper foil with carrier comprising a carrier foil, an organic release interface layer formed on a surface of the carrier foil, and an electrodeposited copper foil layer deposited on the release interface layer, wherein copper microparticles are deposited on the surface of the carrier foil onto which the organic release interface layer and the electrodeposited copper layer are formed.

Abstract translation: 为了提供具有载体的电沉积铜箔，其中可以容易地形成诸如通孔（PTH），间隙通孔（IVH）和盲孔（BVH）的电连接孔。 本发明提供了一种电沉积铜箔，其载体包括载体箔，形成在载体箔表面上的有机释放界面层和沉积在释放界面层上的电沉积铜箔层，其中铜微粒沉积在 其上形成有机释放界面层和电沉积铜层的载体箔。

公开(公告)号：US06335099B1

公开(公告)日：2002-01-01

申请号：US09403503

申请日：1999-10-22

Applicant: Tsutomu Higuchi ,  Mitsuo Suzuki ,  Makoto Dobashi

Inventor： Tsutomu Higuchi ,  Mitsuo Suzuki ,  Makoto Dobashi

IPC: B32B1504

CPC classification number: C25D11/30

Abstract: A corrosion-resistant article of a magnesium material having the gloss of the metal substrate surface comprises an anodic oxide film formed on the external surface of an article of magnesium or a magnesium alloy, which never changes the gloss of the metal substrate and a colorless or colored transparent electrodeposition coating film on the anodic film. Such an article can be prepared by immersing an article of magnesium or a magnesium alloy in an electrolyte containing a phosphate and an aluminate to thus form an anodic oxide film through anodization of the surface of the article and forming a colorless or colored transparent electrodeposition coating film on the anodic film through electrodeposition coating.

Abstract translation: 具有金属基材表面的光泽的镁材料的耐腐蚀制品包括形成在镁或镁合金制品的外表面上的阳极氧化膜，其不会改变金属基材的光泽，并且无色或 在阳极膜上着色的透明电沉积涂膜。 这样的制品可以通过将镁或镁合金制品浸入含有磷酸盐和铝酸盐的电解质中来制备，从而通过阳极氧化制品的表面形成阳极氧化膜并形成无色或有色的透明电沉积涂膜 在阳极膜上通过电沉积涂层。

公开(公告)号：US07808835B2

公开(公告)日：2010-10-05

申请号：US12408896

申请日：2009-03-23

Applicant: Hirokazu Miyazaki ,  Katsuaki Matsui ,  Tsutomu Higuchi

Inventor： Hirokazu Miyazaki ,  Katsuaki Matsui ,  Tsutomu Higuchi

IPC: G11C11/34

CPC classification number: G11C7/067 ,  G11C7/08 ,  G11C16/0441 ,  G11C16/26

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract translation: 在由闪速存储器构成的存储单元阵列中，多个提供了一对具有相互相反值的数据被写入的正存储单元和负存储单元。 连接到数据读取对象的存储单元的位线和I / O线被充电，然后提高连接到数据读取对象存储单元的字线的电位WL。 因此，根据写入的数据，电流在数据读取对象存储单元中流动，因此I / O线的电位BL和电位BLN之一开始下降。 当电位BL和BLN中的一个低于读出放大器的电路阈值时，建立读取数据，并将所建立的读取数据作为读出放大器输出信号SAOUT输出。

公开(公告)号：US20080025110A1

公开(公告)日：2008-01-31

申请号：US11785527

申请日：2007-04-18

Applicant: Hirokazu Miyazaki ,  Katsuaki Matsui ,  Tsutomu Higuchi

Inventor： Hirokazu Miyazaki ,  Katsuaki Matsui ,  Tsutomu Higuchi

IPC: G11C7/06

CPC classification number: G11C7/067 ,  G11C7/08 ,  G11C16/0441 ,  G11C16/26

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract translation: 在由闪速存储器构成的存储单元阵列中，多个提供了一对具有相互相反值的数据被写入的正存储单元和负存储单元。 连接到数据读取对象的存储单元的位线和I / O线被充电，然后提高连接到数据读取对象存储单元的字线的电位WL。 因此，根据写入的数据，电流在数据读取对象存储单元中流动，因此I / O线的电位BL和电位BLN之一开始下降。 当电位BL和BLN中的一个低于读出放大器的电路阈值时，建立读取数据，并将所建立的读取数据作为读出放大器输出信号SAOUT输出。