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    Data storage and replay apparatus
    6.
    发明授权
    Data storage and replay apparatus 有权
    数据存储和重放设备

    公开(公告)号：US08402325B2

    公开(公告)日：2013-03-19

    申请号：US11573192

    申请日：2005-07-22

    Applicant: Sebastian Egner ,  Nicolaas Lambert ,  Ludovicus M. G. M. Tolhuizen ,  Victor M. G. Van Acht ,  Martinus W. Blum

    Inventor： Sebastian Egner ,  Nicolaas Lambert ,  Ludovicus M. G. M. Tolhuizen ,  Victor M. G. Van Acht ,  Martinus W. Blum

    IPC: G06F11/08 ,  G06F11/32

    CPC classification number: G06F11/1012 ,  G06F11/1068 ,  G11B20/1816 ,  G11B20/1833 ,  H03M13/35

    Abstract: A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given the information. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized.

    Abstract translation: 数据存储和重放设备使用存储介质（通常为闪速存储器电路）性能演变的测量来预测从存储介质的区域检索的错误率。 该预测用作在存储数据之前动态选择用于对数据进行编码的ECC的基础。 从多个可用ECC中选择ECC，使得选择最快的可编码ECC，其被预测产生不超过给定信息的预定解码后错误率。 在对通常是音频或视频数据的数据进行解码时，以预定速度进行解码和重放。 在另一个实施例中，动态地选择使用多个ECC存储的数据和ECC，以进行解码，从而可以使输出数据速率最大化，或者可以最大限度地减少重播的功耗。

    FLASH MEMORY ACCESS CIRCUIT
    8.
    发明申请
    FLASH MEMORY ACCESS CIRCUIT 审中-公开
    闪存存取电路

    公开(公告)号：US20100169546A1

    公开(公告)日：2010-07-01

    申请号：US12377675

    申请日：2007-08-13

    Applicant: Victor Martinus Gerardus Van Acht ,  Nicolaas Lambert

    Inventor： Victor Martinus Gerardus Van Acht ,  Nicolaas Lambert

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/28 ,  G06F13/24

    CPC classification number: G06F9/4812

    Abstract: A system comprises an instruction processor (10), a flash memory device (14a), a flash control circuit (14) and a working memory (16). Instructions of an interrupt program are kept stored in the flash memory device (14a). When the instruction processor (10) receives an interrupt signal, the instruction processor (10) executes loading instructions, to cause the flash control circuit (14) to load said instructions of the interrupt program from the flash memory device (14a) into the working memory (16). The instructions of the interrupt program are subsequently executed with the instruction processor (10) from the working memory (16). Preferably it is tested whether a copy of said instructions of the interrupt program is stored in the working memory (16) at the time of the interrupt. If the copy is found stored, execution of said instructions from the copy is started before completing execution of of access instructions that were in progress at the time of the interrupt. If the copy is not found stored, execution of the access instructions is first completed and subsequently the instruction processor (10) executes the loading instructions, followed by execution of the instructions of the copy of interrupt program from the working memory (16).

    Abstract translation: 系统包括指令处理器（10），闪存设备（14a），闪存控制电路（14）和工作存储器（16）。 中断程序的指令被保存在闪速存储器件（14a）中。 当指令处理器（10）接收到中断信号时，指令处理器（10）执行加载指令，使闪存控制电路（14）将来自闪存设备（14a）的中断程序指令加载到工作 记忆（16）。 随后使用来自工作存储器（16）的指令处理器（10）执行中断程序的指令。 优选地，在中断时测试中断程序的所述指令的副本是否存储在工作存储器（16）中。 如果找到存储的副本，则在中断之前完成正在进行的访问指令的执行之前，开始从副本执行所述指令。 如果没有存储副本，则首先完成访问指令的执行，随后指令处理器（10）执行加载指令，随后从工作存储器（16）执行中断程序副本的指令。

    Control of a memory matrix with resistance hysteresis elements
    9.
    发明授权
    Control of a memory matrix with resistance hysteresis elements 有权
    具有电阻滞后元件的存储矩阵的控制

    公开(公告)号：US07580275B2

    公开(公告)日：2009-08-25

    申请号：US11817754

    申请日：2006-03-03

    Applicant: Teunis Jan Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

    Inventor： Teunis Jan Ikkink ,  Pierre Hermanus Woerlee ,  Victor Martinus Van Acht ,  Nicolaas Lambert ,  Albert W. Marsman

    IPC: G11C11/00

    CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C2213/72

    Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

    Abstract translation: 使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。 在第二个 在访问期间，控制电路在执行列选择性更新命令期间从第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）到 在执行全部列更新命令期间的第二空闲状态（12）。 控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II） 分别。

    Encoding of data words using three or more level levels
    10.
    发明授权
    Encoding of data words using three or more level levels 失效
    使用三级或更多级别编码数据字

    公开(公告)号：US07579968B2

    公开(公告)日：2009-08-25

    申请号：US11572807

    申请日：2005-07-19

    Applicant: Victor M. G. Van Acht ,  Nicolaas Lambert ,  Sebastian Egner ,  Hans M. B. Boeve

    Inventor： Victor M. G. Van Acht ,  Nicolaas Lambert ,  Sebastian Egner ,  Hans M. B. Boeve

    IPC: H03M5/02

    CPC classification number: H03M5/04 ,  G11C11/56 ,  G11C11/5621 ,  H03M5/20

    Abstract: A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria. A data signal is generated that represents the input data word by information that identifies the selected groups and an output data word obtained by mapping the digits of each group in the input data word according to the digit map for that group.

    Abstract translation: 数据处理电路包括用于对数据字进行编码的编码器电路，其中每个数字可以具有三个或更多个数字值中的任何一个。 对数据字进行编码，使得数据字中的数字计数满足预定标准（数字计数是在编码数据字中的数字的数量的计数，该数字字代表各自的数字值）。 编码器定义至少两个数字映射，每个数字映射将每个可用数字值的分配定义为相应的不同的输出数字值。 编码器在输入数据字中选择至少两组数字。 每个组与数字映射中的相应一个相关联，这些组被选择，使得当每个数字映射已被选择性地应用于来自其关联组的数字时，相应数字值在数据字中出现的次数的数字计数 将满足预定的标准。 生成数据信号，其通过标识所选择的组的信息和通过根据该组的数字映射映射输入数据字中的每个组的数字而获得的输出数据字来生成输入数据字。

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