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    SIDECAR SRAM FOR HIGH GRANULARITY IN FLOOR PLAN ASPECT RATIO
    31.
    发明申请
    SIDECAR SRAM FOR HIGH GRANULARITY IN FLOOR PLAN ASPECT RATIO 有权
    用于高层建筑的SIDECAR SRAM在平面布置方面比例

    公开(公告)号：US20150364168A1

    公开(公告)日：2015-12-17

    申请号：US14307164

    申请日：2014-06-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

    IPC: G11C7/18 ,  G11C11/406 ,  G06F12/06

    CPC classification number: G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

    Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

    Abstract translation: 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。

    3D memory based address generator for computationally efficient architectures
    32.
    发明授权
    3D memory based address generator for computationally efficient architectures 有权
    基于3D存储器的地址生成器，用于计算高效的架构

    公开(公告)号：US09203671B2

    公开(公告)日：2015-12-01

    申请号：US13648443

    申请日：2012-10-10

    Applicant: Altera Corporation

    Inventor： Lei Xu

    IPC: G06F12/06 ,  H04L27/26 ,  G06F17/14

    CPC classification number: H04L27/263 ,  G06F12/06 ,  G06F12/0623 ,  G06F17/142

    Abstract: Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D symmetric virtual memory may be mapped to memory address in a 1D buffer using an address generation circuit.

    Abstract translation: 公开了用于减小可变大小的快速傅里叶变换（FFT）架构中的存储器使用和增加吞吐量的系统和方法。 特别地，公开了3D对称虚拟存储器来利用可变大小FFT计算中固有的结构。 数据样本可以以利用可变尺寸FFT计算中固有的结构的特定的坐标序列写入3D对称虚拟存储器并从其读取。 可以使用地址生成电路将3D对称虚拟存储器中的存储器位置映射到1D缓冲器中的存储器地址。

    Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices
    33.
    发明申请
    Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices 有权
    本地内部发现和单独选择和共同选择的设备的配置

    公开(公告)号：US20150254192A1

    公开(公告)日：2015-09-10

    申请号：US14438865

    申请日：2013-11-19

    Applicant: RAMBUS INC.

    Inventor： John Eric Linstadt

    IPC: G06F13/16 ,  G06F12/06 ,  G06F12/02

    CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G06F13/1678 ,  G06F2212/7206 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22

    Abstract: A memory controller (110) interfaces with one or more memory devices (120-n) having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices (120-n), the memory controller (110) automatically discovers the connectivity configuration of the one or more memory devices (120-n), including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller (110) configures the memory devices (120-n) according to the discovered connectivity and assigns unique addresses to jointly selected devices.

    Abstract translation: 存储器控制器（110）与具有可配置宽度数据总线的一个或多个存储器件（120-n）和存储器件的数据引脚和存储器控制器的数据引脚之间的可配置连接性相互连接。 在存储器件（120-n）的初始化时，存储器控制器（110）自动发现一个或多个存储器件（120-n）的连接配置，包括单独选择和共同选择的器件。 在发现连接的设备的连接性之后，存储器控制器（110）根据所发现的连接配置存储设备（120-n），并向联合选择的设备分配唯一的地址。

    MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS
    35.
    发明申请
    MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS 有权
    具有大量存储卡的存储器系统和用于控制存储卡的存储器控​​制器

    公开(公告)号：US20150154129A1

    公开(公告)日：2015-06-04

    申请号：US14610836

    申请日：2015-01-30

    Applicant: FUJITSU SEMICONDUCTOR LIMITED

    Inventor： Yoshihiro TAKEMAE

    IPC: G06F13/16 ,  G06F12/02 ,  G11C7/10

    CPC classification number: G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

    Abstract translation: 存储器控制器根据要操作的存储器芯片的操作规范，将从控制器输出的控制器输出信号转换为存储器输入信号，并通过公共总线将结果输出到存储器芯片。 存储器控制器还通过公共总线接收从存储器芯片输出的存储器输出信号，并将接收的信号转换成可接收到控制器的控制器输入信号。 这允许单个存储器控制器访问多种类型的存储器芯片。 结果，存储器控制器可以减小芯片尺寸，降低存储器系统的成本。

    INFORMATION PROCESSING APPARATUS AND MEMORY CONTROL METHOD
    37.
    发明申请
    INFORMATION PROCESSING APPARATUS AND MEMORY CONTROL METHOD 有权
    信息处理装置和存储器控制方法

    公开(公告)号：US20140297989A1

    公开(公告)日：2014-10-02

    申请号：US14224145

    申请日：2014-03-25

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Tomoya Honjo ,  Takahisa Yamamoto

    IPC: G06F12/02

    CPC classification number: G06F12/0607 ,  G06F12/0623

    Abstract: An information processing apparatus comprises a plurality of processor elements, and a memory having a plurality of banks. Statistical information representing an access frequency distribution to each memory area of the memory by the plurality of processor elements is obtained. An allocation process of allocating the banks to the memory areas is performed based on the statistical information.

    Abstract translation: 信息处理装置包括多个处理器元件和具有多个存储体的存储器。 获得表示由多个处理器单元对存储器的每个存储区域的访问频率分布的统计信息。 基于统计信息执行将存储体分配到存储区域的分配处理。

    APPARATUSES AND METHODS FOR PROVIDING DATA FROM MULTIPLE MEMORIES
    38.
    发明申请
    APPARATUSES AND METHODS FOR PROVIDING DATA FROM MULTIPLE MEMORIES 有权
    用于从多个记忆体提供数据的设备和方法

    公开(公告)号：US20140258676A1

    公开(公告)日：2014-09-11

    申请号：US14282787

    申请日：2014-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Yi Chen ,  Yihua Zhang ,  Keith E. Winters

    IPC: G06F12/06

    CPC classification number: G06F12/0615 ,  G06F12/0607 ,  G06F12/0623

    Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

    Abstract translation: 公开了用于提供数据的装置和方法。 示例性装置包括耦合到数据总线的多个存储器。 存储器至少部分地响应于第一地址向数据总线提供数据。 多个存储器在针对在第一地址之后提供给多个存储器的第二地址的感测操作期间进一步提供对应于第一地址的数据的至少一部分到数据总线。 多个存储器中的每一个在不同的时间向数据总线提供对应于第一地址的数据总线。 此外，多个存储器至少部分地响应于地址，至少向数据总线提供2N位的数据，多个存储器中的每一个在不同时间向数据总线提供N位数据。

    Scalable memory system
    40.
    发明授权
    Scalable memory system 有权
    可扩展内存系统

    公开(公告)号：US08671252B2

    公开(公告)日：2014-03-11

    申请号：US13776757

    申请日：2013-02-26

    Applicant: MOSAID Technology Incorporated

    Inventor： Jin-ki Kim ,  Hakjune Oh ,  Hong Beom Pyeon ,  Steven Przybylski

    IPC: G06F12/00

    CPC classification number: G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

    Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统是可扩展的，可以包括任何数量的内存设备，而不会造成任何性能下降或复杂的重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

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