-
31.发明申请公开(公告)号：US20210193237A1
公开(公告)日：2021-06-24
申请号：US17187651
申请日：2021-02-26
发明人： Yali Song , Jianquan Jia , Kaikai You , An Zhang , XiangNan Zhao , Ying Cui , Shan Li , Kaiwei Li , Lei Jin , Xueqing Huang , Meng Lou , Jinlong Zhang
摘要： A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.
-
公开(公告)号：US11024371B2
公开(公告)日：2021-06-01
申请号：US16699115
申请日：2019-11-29
发明人： Ying Cui , Jianquan Jia , Kaikai You
IPC分类号： G11C11/56 , G11C16/04 , H01L27/11556 , G11C16/24
摘要： When programming a memory device which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is perform on two adjacent first and second word lines among the plurality of word lines. Next, an unselected bit line among the plurality of bit lines is pre-charged during a first period after performing the coarse programming on the first word line and the second word line. Also, the channel between the unselected bit line and the second word line is turned on at the start of the first period and turned off prior to the end of the first period. Then, fine programming is performed on the first word line during a second period subsequent to the first period.
-
33.发明授权公开(公告)号：US10991438B1
公开(公告)日：2021-04-27
申请号：US16799806
申请日：2020-02-24
发明人： Yali Song , Jianquan Jia , Kaikai You , An Zhang , XiangNan Zhao , Ying Cui , Shan Li , Kaiwei Li , Lei Jin , Xueqing Huang , Meng Lou , Jinlong Zhang
IPC分类号： G11C16/04 , G11C16/34 , H01L27/11582 , H01L27/11556
摘要： A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.
-
公开(公告)号：US11862230B2
公开(公告)日：2024-01-02
申请号：US17965527
申请日：2022-10-13
发明人： Jianquan Jia , Ying Cui , Kaikai You
IPC分类号： G11C8/00 , G11C11/408 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C11/419
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C11/419
摘要： A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.
-
公开(公告)号：US11705190B2
公开(公告)日：2023-07-18
申请号：US17241010
申请日：2021-04-26
发明人： Ying Cui , Jianquan Jia , Kaikai You
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/24 , H10B41/27
摘要： A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.
-
36.发明授权公开(公告)号：US11676646B2
公开(公告)日：2023-06-13
申请号：US17539133
申请日：2021-11-30
发明人： Shan Li , Kaikai You , Ying Cui , Jianquan Jia , Kaiwei Li , An Zhang
IPC分类号： G11C8/14 , G11C8/08 , G11C7/14 , G11C11/4074 , G11C11/4094 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/30
CPC分类号： G11C8/08 , G11C7/14 , G11C8/14 , G11C11/4074 , G11C11/4094 , G11C16/0425 , G11C16/0466 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/30
摘要： A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level. The controller is further configured to, after the voltage on the select line reaches the second level, drive a voltage on a selected word line of the word lines from the second level to a third level higher than the first level to program the memory cells coupled to the selected word line.
-
公开(公告)号：US20230121846A1
公开(公告)日：2023-04-20
申请号：US18082491
申请日：2022-12-15
发明人： Junbao Wang , Jianquan Jia
摘要： The embodiments of the disclosure provide a control method and apparatus for a memory, and a storage medium. The memory has memory blocks, and each memory block has memory strings. Each of the memory strings includes a channel layer with an N-type doped top region. In a memory block, a bit line erasing voltage is applied to a select bit line, and an erasing prohibition voltage is applied to an unselect bit line. A top select gate voltage lower than the bit line erasing voltage is applied to a top select gate. When a word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word line connected to a memory string corresponding to the select bit line and the unselect bit line, the memory string corresponding to the select bit line is erased.
-
公开(公告)号：US11501822B2
公开(公告)日：2022-11-15
申请号：US17353727
申请日：2021-06-21
发明人： Jianquan Jia , Ying Cui , Kaikai You
IPC分类号： G11C8/00 , G11C11/408 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C11/419
摘要： A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.
-
公开(公告)号：US20220359021A1
公开(公告)日：2022-11-10
申请号：US17869511
申请日：2022-07-20
发明人： Xinlei Jia , Shan Li , Yali Song , Lei Jin , Hongtao Liu , Jianquan Jia , XiangNan Zhao , Yuan-Yuan Min
摘要： A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.
-
公开(公告)号：US11423995B2
公开(公告)日：2022-08-23
申请号：US17186456
申请日：2021-02-26
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
-
-
-
-
-
-
-
-
-
搜索结果
48 条记录 (耗时 0.021 秒)
