公开(公告)号：US20220093741A1

公开(公告)日：2022-03-24

申请号：US17511579

申请日：2021-10-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/167

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

公开(公告)号：US11152515B2

公开(公告)日：2021-10-19

申请号：US16572556

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

公开(公告)号：US20210296182A1

公开(公告)日：2021-09-23

申请号：US17338666

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US10978398B2

公开(公告)日：2021-04-13

申请号：US16732336

申请日：2020-01-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L23/485

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

公开(公告)号：US10854502B2

公开(公告)日：2020-12-01

申请号：US16733214

申请日：2020-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.

公开(公告)号：US10529856B2

公开(公告)日：2020-01-07

申请号：US16028187

申请日：2018-07-05

Applicant: United Microelectronics Corp.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

公开(公告)号：US10062604B2

公开(公告)日：2018-08-28

申请号：US15643488

申请日：2017-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/485

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823864 ,  H01L21/845 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/66719

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

公开(公告)号：US10050146B2

公开(公告)日：2018-08-14

申请号：US14462114

申请日：2014-08-18

Applicant: United Microelectronics Corp.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

公开(公告)号：US20180138088A1

公开(公告)日：2018-05-17

申请号：US15871037

申请日：2018-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.

公开(公告)号：US20180012976A1

公开(公告)日：2018-01-11

申请号：US15695019

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.