公开(公告)号：US20190043809A1

公开(公告)日：2019-02-07

申请号：US15909390

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhee KANG ,  Jiyoung Kim ,  Taejin Yim ,  Jongmin Baek ,  Sanghoon Ahn ,  Hyeoksang Oh ,  Kyu-Hee Han

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5329

Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.

公开(公告)号：US09842803B2

公开(公告)日：2017-12-12

申请号：US15375567

申请日：2016-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

公开(公告)号：US09711453B2

公开(公告)日：2017-07-18

申请号：US15155539

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/288 ,  H01L21/321

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US20170178949A1

公开(公告)日：2017-06-22

申请号：US15374053

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Thomas Oszinda ,  Jongmin Baek ,  Sanghoon Ahn ,  Byunghee Kim ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.

公开(公告)号：US20160322254A1

公开(公告)日：2016-11-03

申请号：US15205168

申请日：2016-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOKYUNG YOU ,  Sanghoon Ahn ,  Sangho Rha ,  Jongmin Baek ,  Nae-In Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.

公开(公告)号：US20160293547A1

公开(公告)日：2016-10-06

申请号：US15155539

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/321 ,  H01L21/02 ,  H01L21/288 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法可以包括在金属图案上和在绝缘层的相邻部分上形成覆盖层，所述覆盖层包括相对于所述绝缘层在所述金属图案上的第一蚀刻选择性，以及第二蚀刻层 在绝缘层的部分上相对于绝缘层的蚀刻选择性。 此外，该方法可以包括通过从绝缘层的部分去除覆盖层来形成与金属图案相邻的凹陷区域。 在从绝缘层的部分去除覆盖层之后，覆盖层的至少一部分可以保留在金属图案的最上表面上。 还提供了相关的半导体器件。

公开(公告)号：US12243777B2

公开(公告)日：2025-03-04

申请号：US18510732

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Lee ,  Hoon Seok Seo ,  Sanghoon Ahn ,  Kyu-Hee Han

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20240421206A1

公开(公告)日：2024-12-19

申请号：US18663186

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonkyu Shin ,  Yongjin Kim ,  Sanghoon Ahn ,  Minkyoung Lee

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction; first and second lower channel layers in a first region and a second region of the active pattern, respectively; first and second upper channel layers on the first and second lower channel layers, respectively; a first source/drain pattern connected to the first and second lower channel layers; an isolation insulating layer on surfaces of the first source/drain pattern in the second direction, where a thickness of opposing edge portions of the isolation insulating layer when viewed in cross section along the first direction is smaller than a thickness of a central portion therebetween; a second source/drain pattern connected to the first and second upper channel layers; and an interlayer insulating layer on the second source/drain patterns and on the isolation insulating layer.

公开(公告)号：US11837618B1

公开(公告)日：2023-12-05

申请号：US16999926

申请日：2020-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesung Hur ,  Taeksoo Jeon ,  Jongmin Baek ,  Sanghoon Ahn ,  Jangho Lee ,  Kyu-Hee Han

IPC: H01L27/146

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14685 ,  H01L27/1463 ,  H01L27/14645

Abstract: An image sensor includes a semiconductor substrate having a plurality of pixel regions arranged in a first direction and a second direction that are parallel to an upper surface of the semiconductor substrate. The first direction is perpendicular to the second direction. A grid structure extends in the first direction and the second direction on the semiconductor substrate to define openings corresponding to a plurality of sub-pixel regions of the plurality of the pixel regions, respectively. Color filters are disposed in the openings of the grid structure, respectively. A protective layer covers sidewalls of the grid structure and bottom surfaces of the color filters. The protective layer includes silicon oxide including carbon (C) or nitrogen (N).

公开(公告)号：US11823952B2

公开(公告)日：2023-11-21

申请号：US18079998

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Lee ,  Hoon Seok Seo ,  Sanghoon Ahn ,  Kyu-Hee Han

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.