公开(公告)号：US20240234542A9

公开(公告)日：2024-07-11

申请号：US18481433

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungheon Lee ,  Donghyun Roh ,  Jangho Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device, includes forming a mask layer on a semiconductor structure having a plurality of gate lines and a plurality of intergate insulating portions, forming an opening that exposes a cut region of the plurality of gate lines in the mask layer, forming a separation hole by removing a portion of a gate capping layer exposed by the opening, forming a pyrolysis material pattern in the separation hole, forming an etch stop layer on an upper surface of the mask layer and on a side wall portion of the separation hole from which the pyrolysis material pattern is removed, while the pyrolysis material pattern is decomposed and removed, and removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.

公开(公告)号：US11764149B2

公开(公告)日：2023-09-19

申请号：US17866782

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US11424182B2

公开(公告)日：2022-08-23

申请号：US17130293

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US12014980B2

公开(公告)日：2024-06-18

申请号：US18446524

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US20210391254A1

公开(公告)日：2021-12-16

申请号：US17155126

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wookyung You ,  Kyeongbeom Park ,  Sungbin Park ,  Suhyun Park ,  Jongmin Baek ,  Jangho Lee ,  Seonghun Lim ,  Deokyoung Jung ,  Kyuhee Han

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.

公开(公告)号：US20240136426A1

公开(公告)日：2024-04-25

申请号：US18481433

申请日：2023-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungheon Lee ,  Donghyun Roh ,  Jangho Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device, includes forming a mask layer on a semiconductor structure having a plurality of gate lines and a plurality of intergate insulating portions, forming an opening that exposes a cut region of the plurality of gate lines in the mask layer, forming a separation hole by removing a portion of a gate capping layer exposed by the opening, forming a pyrolysis material pattern in the separation hole, forming an etch stop layer on an upper surface of the mask layer and on a side wall portion of the separation hole from which the pyrolysis material pattern is removed, while the pyrolysis material pattern is decomposed and removed, and removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.

公开(公告)号：US11837618B1

公开(公告)日：2023-12-05

申请号：US16999926

申请日：2020-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesung Hur ,  Taeksoo Jeon ,  Jongmin Baek ,  Sanghoon Ahn ,  Jangho Lee ,  Kyu-Hee Han

IPC: H01L27/146

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14685 ,  H01L27/1463 ,  H01L27/14645

Abstract: An image sensor includes a semiconductor substrate having a plurality of pixel regions arranged in a first direction and a second direction that are parallel to an upper surface of the semiconductor substrate. The first direction is perpendicular to the second direction. A grid structure extends in the first direction and the second direction on the semiconductor substrate to define openings corresponding to a plurality of sub-pixel regions of the plurality of the pixel regions, respectively. Color filters are disposed in the openings of the grid structure, respectively. A protective layer covers sidewalls of the grid structure and bottom surfaces of the color filters. The protective layer includes silicon oxide including carbon (C) or nitrogen (N).

公开(公告)号：US20220359379A1

公开(公告)日：2022-11-10

申请号：US17866782

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US11139244B2

公开(公告)日：2021-10-05

申请号：US16793366

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho Lee ,  Jongmin Baek ,  Wookyung You ,  Kyu-Hee Han ,  Suhyun Bark

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20240030127A1

公开(公告)日：2024-01-25

申请号：US18446524

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.