公开(公告)号：US20140048939A1

公开(公告)日：2014-02-20

申请号：US13796195

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。

公开(公告)号：US20230215926A1

公开(公告)日：2023-07-06

申请号：US17930145

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jaeung Koo ,  Boun Yoon ,  Ilyoung Yoon ,  Kangchun Lee ,  Seungjae Lee ,  Junhwan Yim ,  Huiteak Hong

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42392

Abstract: A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.

公开(公告)号：US20220310594A1

公开(公告)日：2022-09-29

申请号：US17569363

申请日：2022-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youncheol Jeong ,  Jaeung Koo ,  Kwansung Kim ,  Seungyoon Kim ,  Boun Yoon ,  Jooho Jung ,  Sukbae Joo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure vertically overlapping the active region and the plurality of channel layers on the substrate, extending in a second direction, and including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on an upper surface of the gate electrode, a first source/drain region disposed on a side of the gate structure on the active region and in contact with the plurality of channel layers, an isolation structure intersecting the active region on the substrate, extending in the second direction, and disposed between the first source/drain region and a second source/drain region adjacent to each other, and contact structures in contact with the source/drain regions.

公开(公告)号：US11222897B2

公开(公告)日：2022-01-11

申请号：US16819920

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyesung Park ,  Jinwoo Bae ,  Youngho Koh ,  Jonghyuk Park ,  Boun Yoon ,  Myungjae Jang

IPC: H01L27/108

Abstract: A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

公开(公告)号：US11094586B2

公开(公告)日：2021-08-17

申请号：US16539064

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon Choi ,  Jaeung Koo ,  Kwansung Kim ,  Bo Yun Kim ,  Wandon Kim ,  Boun Yoon ,  Jeonghyuk Yim ,  Yeryung Jeon

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3105

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

公开(公告)号：US20190081102A1

公开(公告)日：2019-03-14

申请号：US15919639

申请日：2018-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kichul Park ,  Ki-Woong Kim ,  Hansol Seok ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/08 ,  H01L43/02 ,  H01F10/32 ,  H01L23/532 ,  H01L23/528 ,  G11C11/16 ,  H01L43/12 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213

Abstract: A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

公开(公告)号：US10153214B2

公开(公告)日：2018-12-11

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung Park ,  Ju-Hyun Kim ,  Hoyoung Kim ,  Boun Yoon ,  TaeYong Kwon ,  Sangkyun Kim ,  Sanghyun Park

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/306 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

公开(公告)号：US20180166529A1

公开(公告)日：2018-06-14

申请号：US15831757

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyesung Park ,  Suyoung Shin ,  Jonghyuk Park ,  Boun Yoon ,  llyoung Yoon ,  Sangyeol Kang ,  SeungHo Park ,  Yanghee Lee ,  Wooin Lee

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/90

Abstract: A semiconductor memory devices and methods of fabricating the same are disclosed. For example, the semiconductor memory device including a semiconductor substrate including a cell area and a peripheral area, a plurality of bottom electrodes on the semiconductor substrate at the cell area, a dielectric layer conformally covering top surfaces and sidewalls of the bottom electrodes, and an upper electrode on the dielectric layer and filling between the bottom electrodes may be provided. A surface roughness of a top surface of the upper electrode may be less than a surface roughness of a side surface of the upper electrode.

公开(公告)号：US09997412B1

公开(公告)日：2018-06-12

申请号：US15646300

申请日：2017-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Ho Bae ,  Jaeseok Kim ,  Hoyoung Kim ,  Boun Yoon ,  KyungTae Lee ,  Kwansung Kim ,  Eunji Park

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.

公开(公告)号：US12207457B2

公开(公告)日：2025-01-21

申请号：US18413434

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.