公开(公告)号：US11532696B2

公开(公告)日：2022-12-20

申请号：US16592842

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gihee Cho ,  Jungoo Kang ,  Sangyeol Kang ,  Hyunsuk Lee

IPC: H01L49/02 ,  H01L27/108

Abstract: Semiconductor devices including a capacitor and methods of forming the same are provided. The semiconductor devices may include a capacitor that include a lower electrode, an upper electrode on the lower electrode, and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region that contacts the dielectric layer, and the doped region of the lower electrode is configured to increase a capacitance of the capacitor.

公开(公告)号：US12119374B2

公开(公告)日：2024-10-15

申请号：US17857383

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee Cho ,  Sangyeol Kang ,  Jungoo Kang ,  Taekyun Kim ,  Jiwoon Park ,  Sanghyuck Ahn ,  Jin-Su Lee ,  Hyun-Suk Lee ,  Hongsik Chae

IPC: H10B12/00 ,  H01L49/02

CPC classification number: H01L28/92 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

公开(公告)号：US11929392B2

公开(公告)日：2024-03-12

申请号：US18057894

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gihee Cho ,  Jungoo Kang ,  Sangyeol Kang ,  Hyunsuk Lee

IPC: H01L49/02 ,  H10B12/00

CPC classification number: H01L28/60 ,  H10B12/315

Abstract: Semiconductor devices including a capacitor and methods of forming the same are provided. The semiconductor devices may include a capacitor that include a lower electrode, an upper electrode on the lower electrode, and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region that contacts the dielectric layer, and the doped region of the lower electrode is configured to increase a capacitance of the capacitor.

公开(公告)号：US11411075B2

公开(公告)日：2022-08-09

申请号：US17189700

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gihee Cho ,  Sangyeol Kang ,  Jungoo Kang ,  Taekyun Kim ,  Jiwoon Park ,  Sanghyuck Ahn ,  Jin-Su Lee ,  Hyun-Suk Lee ,  Hongsik Chae

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

公开(公告)号：US10008505B2

公开(公告)日：2018-06-26

申请号：US15198035

申请日：2016-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Noh Lee ,  Youngkuk Kim ,  Sangyeol Kang ,  Joonsoo Park ,  KiVin Im

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10888

Abstract: A method for manufacturing a semiconductor device may include forming contact pads spaced apart from each other in a first direction on a substrate and between first insulating patterns; forming first holes between the first insulating patterns and having bottom ends adjacent top surfaces of the contact pads; forming second holes between second insulating patterns and overlapping with partial portions of the first holes in a second direction perpendicular to the first direction; and forming a bottom electrode layer including first portions to cover the bottom ends of the first holes and sidewalls of the second holes. In forming the first and second holes, the first and second holes are formed simultaneously.

公开(公告)号：US20200312952A1

公开(公告)日：2020-10-01

申请号：US16592842

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gihee Cho ,  Jungoo Kang ,  Sangyeol Kang ,  Hyunsuk Lee

IPC: H01L49/02

Abstract: Semiconductor devices including a capacitor and methods of forming the same are provided. The semiconductor devices may include a capacitor that include a lower electrode, an upper electrode on the lower electrode, and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region that contacts the dielectric layer, and the doped region of the lower electrode is configured to increase a capacitance of the capacitor.

公开(公告)号：US10453913B2

公开(公告)日：2019-10-22

申请号：US15938234

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuho Cho ,  Sangyeol Kang ,  Suhwan Kim ,  Sunmin Moon ,  Young-Lim Park ,  Jong-Bom Seo ,  Joohyun Jeon

IPC: H01L49/02 ,  H01L21/02

Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.

公开(公告)号：US20180166529A1

公开(公告)日：2018-06-14

申请号：US15831757

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyesung Park ,  Suyoung Shin ,  Jonghyuk Park ,  Boun Yoon ,  llyoung Yoon ,  Sangyeol Kang ,  SeungHo Park ,  Yanghee Lee ,  Wooin Lee

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/90

Abstract: A semiconductor memory devices and methods of fabricating the same are disclosed. For example, the semiconductor memory device including a semiconductor substrate including a cell area and a peripheral area, a plurality of bottom electrodes on the semiconductor substrate at the cell area, a dielectric layer conformally covering top surfaces and sidewalls of the bottom electrodes, and an upper electrode on the dielectric layer and filling between the bottom electrodes may be provided. A surface roughness of a top surface of the upper electrode may be less than a surface roughness of a side surface of the upper electrode.

公开(公告)号：US20230084276A1

公开(公告)日：2023-03-16

申请号：US18057894

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： GIHEE CHO ,  Jungoo Kang ,  Sangyeol Kang ,  Hyunsuk Lee

IPC: H01L49/02

Abstract: Semiconductor devices including a capacitor and methods of forming the same are provided. The semiconductor devices may include a capacitor that include a lower electrode, an upper electrode on the lower electrode, and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region that contacts the dielectric layer, and the doped region of the lower electrode is configured to increase a capacitance of the capacitor.

公开(公告)号：US10854709B2

公开(公告)日：2020-12-01

申请号：US16392097

申请日：2019-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyooho Jung ,  Sangyeol Kang ,  Kyuho Cho ,  Eunsun Kim ,  Hyosik Mun

IPC: H01L21/02 ,  H01L49/02

Abstract: A method of manufacturing a semiconductor device includes forming a first electrode, forming a preliminary dielectric layer on the first electrode, forming a second electrode on the preliminary dielectric layer, and at least partially phase-changing the preliminary dielectric layer to form a dielectric layer. An interfacial energy between the first electrode and the dielectric layer may be less than an interfacial energy between the first electrode and the preliminary dielectric layer.