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    Semiconductor package with dummy pattern not electrically connected to circuit pattern
    31.
    发明授权
    Semiconductor package with dummy pattern not electrically connected to circuit pattern 有权

    公开(公告)号：US12211806B2

    公开(公告)日：2025-01-28

    申请号：US18301606

    申请日：2023-04-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Woo Park ,  Un-Byoung Kang ,  Jong Ho Lee

    IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/485 ,  H01L23/538

    Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    32.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240404972A1

    公开(公告)日：2024-12-05

    申请号：US18799579

    申请日：2024-08-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seyeong SEOK ,  Un-Byoung Kang ,  Chungsun Lee

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

    Abstract: A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure.

    Semiconductor package
    35.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11676887B2

    公开(公告)日：2023-06-13

    申请号：US17318227

    申请日：2021-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeonggi Jin ,  Gyuho Kang ,  Solji Song ,  Un-Byoung Kang ,  Ju-Il Choi

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

    Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

    Semiconductor packages
    36.
    发明授权
    Semiconductor packages 有权

    公开(公告)号：US11621250B2

    公开(公告)日：2023-04-04

    申请号：US17571796

    申请日：2022-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

    IPC: H01L25/065 ,  H01L23/00

    Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

    STACKED SEMICONDUCTOR PACKAGE
    37.
    发明申请
    STACKED SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230076511A1

    公开(公告)日：2023-03-09

    申请号：US18054530

    申请日：2022-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    38.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220157757A1

    公开(公告)日：2022-05-19

    申请号：US17329980

    申请日：2021-05-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seyeong Seok ,  Un-Byoung Kang ,  Chungsun Lee

    IPC: H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

    Abstract: A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure.

    Semiconductor package
    39.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11114364B2

    公开(公告)日：2021-09-07

    申请号：US16223642

    申请日：2018-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hee-Jeong Kim ,  Juhyun Lyu ,  Un-Byoung Kang ,  Jongho Lee

    IPC: H01L23/373 ,  H01L23/31 ,  H01L23/367

    Abstract: Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment.

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