公开(公告)号：US06493258B1

公开(公告)日：2002-12-10

申请号：US09618237

申请日：2000-07-18

Applicant: Yong Lu ,  Theodore Zhu ,  Romney R. Katti

Inventor： Yong Lu ,  Theodore Zhu ,  Romney R. Katti

IPC: G11C1100

CPC classification number: G11C11/5607 ,  G11C7/06 ,  G11C11/15

Abstract: A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.

公开(公告)号：US5436861A

公开(公告)日：1995-07-25

申请号：US905878

申请日：1992-06-29

Applicant: Romney R. Katti ,  Henry L. Stadler ,  Jiin-chuan Wu

Inventor： Romney R. Katti ,  Henry L. Stadler ,  Jiin-chuan Wu

IPC: G11C19/08

CPC classification number: G11C19/0866 ,  G11C19/0858

Abstract: A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

Abstract translation: 公开了用于垂直布洛赫线（VBL）存储器的新的读门设计，其提供比现有读门设计更大的操作裕度。 在现有的读门设计中，电流被应用于所有条纹。 包含VBL对的条纹被切碎，而不包含VBL对的条带不被切碎。 然后通过检查气泡的存在或不存在来检测信息。 斩波电流幅度的裕度非常小，有时不存在。 还公开了一种读取Vertical Bloch Line存储器的新方法。 代替使用壁手性来分离两个二进制状态，使用条带头的空间偏转。 本文还公开了一种紧凑型存储器，其使用垂直Bloch线（VBL）存储器技术来提供数据存储。 使用VBL存储层堆叠形式的三维布置来实现高容量存储密度。 通过并行操作所有层来实现高数据传输速率。 通过使用霍尔效应感测和通过法拉第效应的光学感测来访问三维封装内的数据，由于每层内的并行操作，可以实现更高的数据传输速率。

公开(公告)号：US5329480A

公开(公告)日：1994-07-12

申请号：US993012

申请日：1992-12-18

Applicant: Jiin-Chuan Wu ,  Henry L. Stadler ,  Romney R. Katti

Inventor： Jiin-Chuan Wu ,  Henry L. Stadler ,  Romney R. Katti

IPC: G11C11/14 ,  G11C11/18

CPC classification number: G11C11/14 ,  G11C11/18

Abstract: A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a "0" or "1" state. The element remains in the "0" or "1" state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

Abstract translation: 可以通过磁 - 霍尔效应（M-H）元件的阵列来实现非易失磁性随机存取存储器。 存储功能由具有面内，单轴各向异性和面内双极残余磁化状态的矩形薄膜铁磁材料实现。 薄膜磁性元件被局部施加的磁场磁化，其方向用于形成“0”或“1”状态。 该元素保持在“0”或“1”状态，直到应用切换字段来更改其状态。 存储的信息被霍尔效应传感器所检测，该传感器感测来自磁存储元件的边缘场。 用于寻址每个单元的电路设计包括用于提供选定极性的电流的晶体管开关，以通过覆盖电池的磁性元件的单独导体来存储二进制数字。 为了读出存储的二进制数字，采用晶体管开关来提供一系列连续串联的霍尔效应传感器的电流，并使差分电压放大器与串联的所有霍尔效应传感器相连。 为了避免由于分流电流而导致的读出电压误差，通过同一列中的其他单元的霍尔效应传感器的电阻负载，至少有一个晶体管开关被提供在每一行不被打开的每对相邻单元之间，除了 在所选单元格的行中。

公开(公告)号：US20130250662A1

公开(公告)日：2013-09-26

申请号：US13429692

申请日：2012-03-26

Applicant: Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

Inventor： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC: G11C11/16 ,  H01L21/8246

CPC classification number: H01L23/57 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L23/573 ,  H01L27/228 ,  H01L43/02 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

Abstract: A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir.

Abstract translation: 磁阻随机存取存储器（MRAM）管芯可以包括MRAM单元，由MRAM管芯限定的储存器和设置在贮存器中的化学物质。 储存器的至少一个边界可以被配置为响应于试图篡改MRAM管芯而被损坏，使得当储存器的至少一个边界被损坏时，至少一些化学物质从贮存器释放。 在一些实例中，当化学品从储存器中释放时，至少一些化学物质被配置为接触和改变或损坏MRAM单元的至少一部分。

公开(公告)号：US20130241014A1

公开(公告)日：2013-09-19

申请号：US13419109

申请日：2012-03-13

Applicant: Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

Inventor： Romney R. Katti ,  James L. Tucker ,  Anuj Kohli

IPC: H01L29/82 ,  H01L43/12

CPC classification number: H01L23/57 ,  G06F21/86 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1695 ,  H01L23/573 ,  H01L27/222 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/00

Abstract: A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.

Abstract translation: 磁阻随机存取存储器（MRAM）封装可以包括MRAM裸片，限定空腔和外表面的封装以及设置在封装体的腔体内或外表面上的磁性安全结构。 MRAM管芯可以设置在封装的空腔中，并且磁性安全结构可以包括至少三层，包括永磁层和软磁性层。

公开(公告)号：US08399964B2

公开(公告)日：2013-03-19

申请号：US12861442

申请日：2010-08-23

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: H01L23/552

CPC classification number: H05K9/0075 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15156 ,  H01L2924/16195 ,  H05K9/0088 ,  H01L2224/45099

Abstract: A magnetic shield is presented. The shield may be used to protect a microelectronic device from stray magnetic fields. The shield includes at least two layers. A first layer includes a magnetic material that may be used to block DC magnetic fields. A second layer includes a conductive material that may be used to block AC magnetic fields. Depending on the type of material that the first and second layers include, a third layer may be inserted in between the first and second layers. The third layer may include a non-conductive material that may be used to ensure that separate eddy current regions form in the first and second layers.

Abstract translation: 提供磁屏蔽。 屏蔽可用于保护微电子器件免受杂散磁场的影响。 屏蔽层至少包括两层。 第一层包括可用于阻挡直流磁场的磁性材料。 第二层包括可用于阻挡交流磁场的导电材料。 根据第一和第二层包括的材料的类型，第三层可以插入在第一层和第二层之间。 第三层可以包括非导电材料，其可用于确保在第一层和第二层中形成单独的涡流区。

公开(公告)号：US08358154B2

公开(公告)日：2013-01-22

申请号：US12916046

申请日：2010-10-29

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: H03K19/20 ,  H03K19/094 ,  G11C11/22

CPC classification number: H03K19/16 ,  G11C11/161

Abstract: This disclosure is directed to a magnetic logic gate for implementing a combinational logic function. The magnetic logic gate may include a write circuit configured to apply a spin-polarized current to the magnetoresistive device such that a resulting programmed magnetization state of the magnetoresistive device corresponds to a logic input value of a combinational logic function implemented by the magnetic logic device. The magnetic logic gate may further include a read circuit configured to generate a logic output value for the combinational logic function based on the programmed magnetization state in response to the write circuit applying the spin-polarized current to the magnetoresistive device.

Abstract translation: 本公开涉及用于实现组合逻辑功能的磁逻辑门。 磁逻辑门可以包括写电路，其被配置为将自旋极化电流施加到磁阻器件，使得磁阻器件的结果编程磁化状态对应于由磁逻辑器件实现的组合逻辑功能的逻辑输入值。 磁逻辑门还可以包括读电路，其被配置为响应于施加自旋极化电流到磁阻器件的写电路，基于编程的磁化状态来生成用于组合逻辑功能的逻辑输出值。

公开(公告)号：US20120155155A1

公开(公告)日：2012-06-21

申请号：US12971244

申请日：2010-12-17

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: G11C11/00

CPC classification number: G11C7/04 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697

Abstract: This disclosure describes write current temperature compensation techniques for use in programming a data storage device that includes one or more memory cells. The techniques may include programming a programmable magnetization state of a magnetoresistive device included within a resistance network based on a signal indicative of the operating temperature of a magnetic memory cell. The techniques may further include generating a write current having a magnitude that is determined at least in part by the programmable magnetization state of the magnetoresistive device. The techniques may further include supplying the write current to the magnetic memory cell for programming a programmable magnetization state of the magnetic memory cell.

Abstract translation: 本公开描述了用于编程包括一个或多个存储器单元的数据存储设备的写入当前温度补偿技术。 这些技术可以包括基于指示磁存储器单元的工作温度的信号来编程包括在电阻网络内的磁阻器件的可编程磁化状态。 这些技术可以进一步包括产生具有至少部分由磁阻器件的可编程磁化状态确定的幅度的写入电流。 这些技术可以进一步包括向磁性存储单元提供写入电流以编程磁性存储单元的可编程磁化状态。

公开(公告)号：US20120106233A1

公开(公告)日：2012-05-03

申请号：US12916238

申请日：2010-10-29

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: G11C11/22 ,  H01L43/12 ,  H01L29/82

CPC classification number: H01L27/222 ,  G11C11/161 ,  H03K19/18

Abstract: A system includes a continuous thin-film ferromagnetic layer, N magnetic tunnel junction (MTJ) devices, and N write structures. The continuous thin-film ferromagnetic layer includes N modified regions. Each of the N modified regions is configured to stabilize a magnetic domain wall located in the continuous thin-film ferromagnetic layer. Each of the N MTJ devices includes one of N portions of the continuous thin-film ferromagnetic layer. Adjacent MTJ devices of the N MTJ devices are separated by one of the N modified regions. Each of the N write structures is configured to receive current and generate a magnetic field that magnetizes a different one of the N portions of the continuous thin-film ferromagnetic layer. N is an integer greater than 2.

Abstract translation: 一种系统包括连续的薄膜铁磁层，N磁性隧道结（MTJ）器件和N个写入结构。 连续薄膜铁磁层包括N个改性区域。 N个修饰区域中的每一个被配置为稳定位于连续薄膜铁磁层中的磁畴壁。 N MTJ器件中的每一个包括连续薄膜铁磁层的N个部分中的一个。 N个MTJ设备的相邻MTJ设备由N个修改区域之一分隔开。 N个写入结构中的每一个被配置为接收电流并且产生使连续薄膜铁磁层的N个部分中的不同一个磁化的磁场。 N是大于2的整数。

公开(公告)号：US20120105101A1

公开(公告)日：2012-05-03

申请号：US12916046

申请日：2010-10-29

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: H03K19/20

CPC classification number: H03K19/16 ,  G11C11/161

Abstract: This disclosure is directed to a magnetic logic gate for implementing a combinational logic function. The magnetic logic gate may include a write circuit configured to apply a spin-polarized current to the magnetoresistive device such that a resulting programmed magnetization state of the magnetoresistive device corresponds to a logic input value of a combinational logic function implemented by the magnetic logic device. The magnetic logic gate may further include a read circuit configured to generate a logic output value for the combinational logic function based on the programmed magnetization state in response to the write circuit applying the spin-polarized current to the magnetoresistive device.

Abstract translation: 本公开涉及用于实现组合逻辑功能的磁逻辑门。 磁逻辑门可以包括写电路，其被配置为将自旋极化电流施加到磁阻器件，使得磁阻器件的结果编程磁化状态对应于由磁逻辑器件实现的组合逻辑功能的逻辑输入值。 磁逻辑门还可以包括读电路，其被配置为响应于施加自旋极化电流到磁阻器件的写电路，基于编程的磁化状态来生成用于组合逻辑功能的逻辑输出值。