公开(公告)号：US20200257501A1

公开(公告)日：2020-08-13

申请号：US16782777

申请日：2020-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto YABUUCHI

IPC: G06F7/544 ,  H01L23/528 ,  H01L27/11 ,  G11C11/418 ,  G11C11/419

Abstract: A semiconductor device that can reduce power consumption while improving the accuracy of learning and inference is provided. The semiconductor device is connected to data lines PBL, NBL, and comprises a product operation memory cell 1 for storing data of ternary value and performing a product-sum operation between a stored data and an input data INP and a data in the data lines PBL, NBL.

公开(公告)号：US20190198107A1

公开(公告)日：2019-06-27

申请号：US16192377

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto YABUUCHI ,  Koji NII

IPC: G11C15/04

Abstract: A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.

公开(公告)号：US20190147947A1

公开(公告)日：2019-05-16

申请号：US16248489

申请日：2019-01-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI

IPC: G11C11/419

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

公开(公告)号：US20190043582A1

公开(公告)日：2019-02-07

申请号：US16030136

申请日：2018-07-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto YABUUCHI

IPC: G11C15/04 ,  H01L23/528 ,  H01L27/105 ,  H01L23/552 ,  H01L27/088

Abstract: A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.

公开(公告)号：US20180026024A1

公开(公告)日：2018-01-25

申请号：US15719830

申请日：2017-09-29

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20170309326A1

公开(公告)日：2017-10-26

申请号：US15513138

申请日：2015-03-31

Applicant: Renesas Electronics Corporation

Inventor： Yohei SAWADA ,  Makoto YABUUCHI ,  Yuichiro ISHII

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413

Abstract: A semiconductor device includes a SRAM circuit. The SRAM circuit includes: a memory array having a plurality of memory cells arranged in a matrix; a ground interconnection commonly connected to each of the memory cells; and a first potential control circuit for controlling a potential of the ground interconnection depending on an operation mode. The first potential control circuit includes a first NMOS transistor and a first PMOS transistor connected in parallel to each other between a around node providing a ground potential and the ground interconnection.

公开(公告)号：US20170263307A1

公开(公告)日：2017-09-14

申请号：US15606903

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/04 ,  G11C5/148

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

公开(公告)号：US20170076783A1

公开(公告)日：2017-03-16

申请号：US15211364

申请日：2016-07-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Shinji TANAKA

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/04 ,  G11C5/148

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

Abstract translation: 半导体存储装置包括多个存储模块，其中可以基于第一和第二控制信号来设置和取消多个低功耗模式。 多个存储器模块的至少一部分存储器模块具有将输入的第一控制信号传播到后级存储器模块的传播路径。 第二控制信号并行地输入到多个存储器模块中的每一个。 基于通过传播路径传播的第一控制信号和第二控制信号的组合来执行每个存储器模块的第一低功耗模式的设置和取消。 根据传播的第一控制信号，依次执行每个存储器模块的设置和取消其中关闭电源的区域与第一低功耗模式的区域不同的第二低功耗模式 传播路径。

公开(公告)号：US20170076760A1

公开(公告)日：2017-03-16

申请号：US15211298

申请日：2016-07-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI

IPC: G11C7/10 ,  G11C7/22 ,  H01L27/088

CPC classification number: H01L27/0886 ,  G11C7/10 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924

Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

Abstract translation: 在不过度增加电路面积的情况下控制数据保持时间。 半导体器件包括数据缓冲器和由鳍形成的触发器。 作为延迟线，在从数据缓冲器的数据输出节点到触发器的数据输入节点的数据信号路径中提供与鳍片的栅电极在同一层中的栅极布线。

公开(公告)号：US20160240246A1

公开(公告)日：2016-08-18

申请号：US15134981

申请日：2016-04-21

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.