公开(公告)号：US20190066746A1

公开(公告)日：2019-02-28

申请号：US15688212

申请日：2017-08-28

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01F10/32 ,  G11C11/15 ,  H01L43/08

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

公开(公告)号：US10210920B1

公开(公告)日：2019-02-19

申请号：US15937317

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Xia Li ,  Wah Nam Hsu ,  Seung Hyuk Kang

IPC: H01L43/08 ,  G11C11/00 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  G11C17/16

Abstract: Magnetic tunnel junction (MTJ) devices with varied breakdown voltages in different memory arrays fabricated in a same semiconductor die to facilitate different memory applications are disclosed. In exemplary aspects disclosed herein, MTJ devices are fabricated in a semiconductor die to provide at least two different memory arrays. MTJ devices in each memory array are fabricated to have different breakdown voltages. For example, it may be desired to fabricate a One-Time-Programmable (OTP) memory array in the semiconductor die using MTJ devices having a first, lower breakdown voltage, and a separate magneto-resistive random access memory (MRAM) in a same semiconductor die with MTJ devices having a higher breakdown voltage. Thus, in this example, lower breakdown voltage MTJ devices in OTP memory array require less voltage to program, while higher breakdown voltage MTJ devices in MRAM can maintain a desired write operation margin to avoid or reduce write operations causing dielectric breakdown.

公开(公告)号：US09704919B1

公开(公告)日：2017-07-11

申请号：US15192068

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Wei-Chuan Chen ,  Jimmy Jianan Kan ,  Seung Hyuk Kang

IPC: H01L29/66 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L23/528 ,  H01L23/522 ,  H01L43/12 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L27/228 ,  G11C11/16 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L43/12

Abstract: High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed. In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transistor and a magnetic tunnel junction (MTJ) therein. The coupling column is disposed across a plurality of interconnection layers. In one aspect, the coupling column comprises a high aspect ratio via. In another aspect, the high aspect ratio via is connected directly between a drain contact coupled to a drain of the access transistor and to an end electrode of the MTJ such that no interconnection line and/or interconnection island is provided in the coupling column. In certain aspects, the coupling column may be disposed between an interconnection line and an adjacent interconnection line without increasing an existing interconnection line pitch, thus allowing for a reduction in MRAM bit cell pitch.

公开(公告)号：US09349939B2

公开(公告)日：2016-05-24

申请号：US14286518

申请日：2014-05-23

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Chando Park ,  Wei-Chuan Chen

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a spacer on an exposed side portion of the MTJ device. The method further includes forming an etch-resistant protective coating associated with the MTJ device. The etch-resistant protective coating provides greater etch resistance than the spacer.

Abstract translation: 形成磁性隧道结（MTJ）装置的方法包括在MTJ装置的暴露侧部分上形成间隔物。 该方法还包括形成与MTJ装置相关联的耐蚀刻保护涂层。 耐蚀刻保护涂层比间隔物提供更大的耐蚀刻性。

公开(公告)号：US20160064391A1

公开(公告)日：2016-03-03

申请号：US14469341

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Woo Tag Kang ,  Changhan Hobie Yun ,  Wei-Chuan Chen

IPC: H01L27/115 ,  G11C11/409 ,  G11C11/22 ,  H01L27/108

CPC classification number: H01L27/11507 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/409 ,  H01G7/06 ,  H01L27/10805 ,  H01L27/10808 ,  H01L27/10897 ,  H01L27/11512 ,  H01L27/11514 ,  H01L28/91

Abstract: A memory cell includes a capacitor that includes a first metal layer and a second metal layer. The capacitor includes a ferroelectric layer disposed between the first metal layer and the second metal layer. The ferroelectric layer is a single layer of a bi-stable asymmetric crystalline material.

Abstract translation: 存储单元包括包括第一金属层和第二金属层的电容器。 电容器包括设置在第一金属层和第二金属层之间的铁电层。 铁电层是单层双稳态不对称结晶材料。

公开(公告)号：US09214624B2

公开(公告)日：2015-12-15

申请号：US13770526

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Wei-Chuan Chen ,  Seung H. Kang

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  G11C11/15 ,  G11C11/16

CPC classification number: H01L43/10 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.

Abstract translation: 垂直磁隧道结（MTJ）装置包括沉积在隧道势垒层和参考层之间的隧道磁阻（TMR）增强缓冲层。在TMR增强缓冲层和参考层之间沉积非晶合金间隔物以增强TMR非晶态 合金间隔块阻挡面心立方（fcc）取向钉扎层的模板效应，并且在钉扎层和TMR增强缓冲层之间提供强耦合，以确保完全垂直磁化。

公开(公告)号：US08796046B2

公开(公告)日：2014-08-05

申请号：US14036354

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L29/82 ,  G11C11/16 ,  H01L27/22 ,  H01L27/115 ,  H01L43/08

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L23/552 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.

Abstract translation: 提供了用于屏蔽屏蔽非易失性存储器的方法和装置，例如屏蔽磁性隧道结（MTJ）装置与磁通量。 在一个示例中，屏蔽层邻近MTJ器件的电极形成，使得屏蔽层基本上围绕电极的表面，并且金属线耦合到屏蔽层。 金属线可以通过通孔耦合到屏蔽层。

公开(公告)号：US10608174B2

公开(公告)日：2020-03-31

申请号：US16523682

申请日：2019-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32 ,  H01L43/10

Abstract: Double-patterned magneto-resistive random access memory (MRAM) for reducing magnetic tunnel junction (MTJ) pitch for increased MRAM bit cell density is disclosed. In one aspect, to fabricate MTJs in an MRAM array with reduced MTJ row pitch, a first patterning process is performed to provide separation areas in an MTJ layer between what will become rows of fabricated MTJs, which facilitates MTJs in a given row sharing a common bottom electrode. This reduces the etch depth and etching time needed to etch the individual MTJs in a subsequent step, can reduce lateral projections of sidewalls of the MTJs, thereby relaxing the pitch between adjacent MTJs, and may allow an initial MTJ hard mask layer to be reduced in height. A subsequent second patterning process is performed to fabricate individual MTJs. Additional separation areas are etched between free layers of adjacent MTJs in a given row to fabricate the individual MTJs.

公开(公告)号：US10460817B2

公开(公告)日：2019-10-29

申请号：US15817474

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Wei-Chuan Chen

IPC: G11C7/00 ,  G11C16/34 ,  G11C11/56 ,  G11C14/00 ,  G11C16/04 ,  H01L27/108 ,  H01L29/792 ,  H01L45/00 ,  G06N3/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/54 ,  G06N3/04 ,  G06N3/08 ,  G11C7/18 ,  G11C8/14 ,  H03K19/177

Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

公开(公告)号：US10431278B2

公开(公告)日：2019-10-01

申请号：US15676957

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wah Nam Hsu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C5/14 ,  G11C7/04 ,  G11C29/50 ,  H01L27/22 ,  H01L43/08

Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.