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    STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT
    31.
    发明申请
    STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT 有权
    结构和方法来组织身体接触

    公开(公告)号：US20130134527A1

    公开(公告)日：2013-05-30

    申请号：US13748942

    申请日：2013-01-24

    申请人： International Business Machines Corporation

    发明人： Chengwen Pei ,  Roger Allen Booth ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L29/49

    CPC分类号： H01L29/49 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

    摘要： A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

    摘要翻译： 公开了一种在晶体管上制造体接触的结构和方法。 该方法包括在处理晶片上形成具有晶体管的半导体结构。 然后将结构反转，并移除手柄晶片。 然后在倒置位置的晶体管上形成硅化物体接触。 身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。

    ASYMMETRIC FET
    34.
    发明申请
    ASYMMETRIC FET 有权
    不对称FET

    公开(公告)号：US20160276437A1

    公开(公告)日：2016-09-22

    申请号：US15168446

    申请日：2016-05-31

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L23/528 ,  H01L29/167 ,  H01L29/165

    CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31053 ,  H01L23/485 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66356 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    摘要： After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.

    摘要翻译： 在不被栅极结构覆盖的半导体部分的凹面上形成第一侧外延半导体区域和第二侧外延半导体区域之后，形成至少一个介电层以覆盖第一侧和第二侧外延半导体区域， 侧外延半导体区域和栅极结构。 在所述至少一个电介质层内形成第二侧接触开口以暴露所述第二侧外延半导体区域的整体。 暴露的第二侧外延半导体区域可以由具有不同于第一侧外延半导体区域的组成的新的第二侧外延半导体区域代替，或者可以通过附加的掺杂剂掺杂，从而产生非对称的第一侧外延半导体区域 和第二侧外延半导体区域。 第一侧外延半导体区域和第二侧外延半导体区域中的每一个可以用作晶体管的源极或漏极。

    Metal trench capacitor and improved isolation and methods of manufacture
    35.
    发明授权
    Metal trench capacitor and improved isolation and methods of manufacture 有权
    金属沟槽电容器和改进的隔离和制造方法

    公开(公告)号：US09287272B2

    公开(公告)日：2016-03-15

    申请号：US14467580

    申请日：2014-08-25

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L29/66 ,  H01L21/74 ,  H01L21/762 ,  H01L27/12 ,  H01L27/06

    CPC分类号： H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

    摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

    摘要翻译： 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

    Multilayer MIM capacitor
    36.
    发明授权
    Multilayer MIM capacitor 有权

    公开(公告)号：US09224801B2

    公开(公告)日：2015-12-29

    申请号：US14532281

    申请日：2014-11-04

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L21/3213

    CPC分类号： H01L28/40 ,  H01L21/32134 ,  H01L28/86 ,  H01L28/90 ,  H01L28/91

    摘要： An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

    Self-aligned devices and methods of manufacture
    37.
    发明授权
    Self-aligned devices and methods of manufacture 有权
    自对准装置和制造方法

    公开(公告)号：US09159578B2

    公开(公告)日：2015-10-13

    申请号：US14188814

    申请日：2014-02-25

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/302 ,  B44C1/22 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/3213

    CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the patterned line to the substrate.

    摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和图案化线的图案转移到衬底。

    Embedded DRAM for extremely thin semiconductor-on-insulator
    38.
    发明授权
    Embedded DRAM for extremely thin semiconductor-on-insulator 有权
    嵌入式DRAM，用于极薄的绝缘体上半导体

    公开(公告)号：US09059213B2

    公开(公告)日：2015-06-16

    申请号：US13845506

    申请日：2013-03-18

    申请人： International Business Machines Corporation

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/8242 ,  H01L27/12 ,  H01L29/94 ,  H01L29/66 ,  H01L27/108 ,  H01L21/84

    CPC分类号： H01L29/66742 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

    摘要翻译： 填充深沟槽的节点电介质和导电沟槽填充区域凹陷到与绝缘体上半导体（SOI）层的顶表面基本上共面的深度。 浅沟槽隔离部分形成在深沟槽的上部的一侧上，而深沟槽的上部的另一侧提供导电填充区域的半导体材料的暴露表面。 执行选择性外延工艺以沉积升高的源极区域和升高的带状区域。 升高的源极区域直接形成在SOI层内的平坦的源极区域上，并且凸起的带区域直接形成在导电填充区域上。 升高的带区域接触升高的源极区域，以在平面源极区域和导电填充区域之间提供导电路径。

    Rare-earth oxide isolated semiconductor fin
    39.
    发明授权
    Rare-earth oxide isolated semiconductor fin 有权
    稀土氧化物隔离半导体鳍片

    公开(公告)号：US09058987B2

    公开(公告)日：2015-06-16

    申请号：US14336407

    申请日：2014-07-21

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/02488 ,  H01L21/02513 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02642 ,  H01L29/66795 ,  H01L29/785

    摘要： A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.

    摘要翻译： 电介质模板层沉积在衬底上。 通过使用图案化掩模层的各向异性蚀刻，在电介质模板层内形成线沟槽。 图案化掩模层可以是图案化的光致抗蚀剂层，或者通过其它图像转印方法形成的图案化的硬掩模层。 通过选择性稀土氧化物外延法，用外延稀土氧化物材料填充每个线沟槽的下部。 通过选择性半导体外延工艺，用外延半导体材料填充每个线沟槽的上部。 电介质模板层被凹入以形成介电材料层，该电介质材料层在散热片结构之间提供横向电隔离，其中每一个包括稀土氧化物翅片部分和半导体散热片部分的堆叠。

    SELF-ALIGNED DEVICES AND METHODS OF MANUFACTURE
    40.
    发明申请
    SELF-ALIGNED DEVICES AND METHODS OF MANUFACTURE 有权
    自对准设备及其制造方法

    公开(公告)号：US20140170854A1

    公开(公告)日：2014-06-19

    申请号：US14188814

    申请日：2014-02-25

    申请人： International Business Machines Corporation

    发明人： Roger A. BOOTH, JR. ,  Kangguo CHENG ,  Joseph Ervin ,  Chengwen PEI ,  Ravi M. TODI ,  Geng WANG

    IPC分类号： H01L21/3105

    CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the patterned line to the substrate.

    摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和图案化线的图案转移到衬底。