公开(公告)号：US20100244186A1

公开(公告)日：2010-09-30

申请号：US12722920

申请日：2010-03-12

Applicant: Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI ,  Tomoko FUJIWARA

Inventor： Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI ,  Tomoko FUJIWARA

IPC: H01L27/10 ,  H01L21/822 ,  G11C17/16

CPC classification number: H01L27/1021 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film.

Abstract translation: 一种非易失性半导体存储器件，包括：堆叠结构单元，包括沿第一方向堆叠的多个堆叠的元件单元，每个堆叠元件单元包括由垂直于第一元件垂直设置的第一导电类型的半导体制成的第一导电膜 方向和与第一导电膜在第一方向上堆叠的第一绝缘膜; 所述半导体柱在所述第一方向上穿透所述层叠结构单元，并且包括第二导电类型的导电区域，所述半导体柱包括与所述第一导电膜相对的第一区域，以及设置在所述第一区域之间的第二区域， 所述第一方向，所述第二区域具有与所述第一区域的电阻不同的电阻; 以及设置在所述半导体柱和所述第一导电膜之间的第二绝缘膜。

公开(公告)号：US20100244119A1

公开(公告)日：2010-09-30

申请号：US12724713

申请日：2010-03-16

Applicant: Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract translation: 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。

公开(公告)号：US20100181612A1

公开(公告)日：2010-07-22

申请号：US12638480

申请日：2009-12-15

Applicant: Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

Inventor： Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

IPC: H01L29/788 ,  H01L21/205 ,  H01L21/336

CPC classification number: H01L29/788 ,  G11C16/0458 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1156 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

Abstract: A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.

Abstract translation: 非易失性半导体存储器件包括：通过交替堆叠多个层间绝缘膜和多个控制栅电极来形成堆叠体; 在层叠体中形成沿堆叠方向延伸的通孔; 通过通孔蚀刻面向通孔的层间绝缘膜的一部分以除去该部分; 形成去除部分; 在通孔的内表面和除去层间绝缘膜的部分之间形成第一绝缘膜; 在除去层间绝缘膜的部分中形成浮栅电极; 形成第二绝缘膜，以覆盖面对通孔的浮栅电极的一部分; 并将半导体柱埋在通孔中。

公开(公告)号：US5978265A

公开(公告)日：1999-11-02

申请号：US746176

申请日：1991-08-15

Applicant: Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

Inventor： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

IPC: G11C17/12 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.

Abstract translation: 公开了一种电可擦除可编程只读存储器，其具有连接到设置在半导体衬底上的并行位线的可编程存储器单元。 存储单元包括NAND单元块，每个NAND单元具有存储单元晶体管的串联阵列。 并行字线分别连接到存储单元晶体管的控制栅极。 在数据写入模式中，包括所选择的存储单元的某个NAND单元块中的选择晶体管被导通以将特定单元块连接到与其相关联的相应位线。 在这种条件下，电子被隧道注入到所选择的存储单元晶体管的浮动栅极中，并且特定晶体管的阈值增加到正值。 因此，逻辑数据被写入所选择的存储单元晶体管中。 通过将其浮置栅极中累积的载流子放电到其漏极或衬底来擦除所选择的单元晶体管中的数据，使得某个晶体管的阈值降低为负值。

公开(公告)号：US5602789A

公开(公告)日：1997-02-11

申请号：US518024

申请日：1995-08-22

Applicant: Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

Inventor： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC: G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC classification number: G11C16/3418 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

Abstract: An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.

Abstract translation: 用于存储多级数据的EEPROM包括存储单元阵列，其中电可擦除可编程存储器单元被排列成矩阵，并且每个存储单元具有至少三个存储状态，第一存储单元写入数据的写入电路 以及分别由读出放大器，数据锁存电路和检测电路构成的第二写入验证装置，用于分别验证存储器单元的写入不足状态和存储单元的过量写入状态，附加写入电路 在写入状态不足的情况下向存储器单元写入数据，以及附加擦除电路，用于在超量写入状态下从存储单元附加擦除数据。

公开(公告)号：US5528547A

公开(公告)日：1996-06-18

申请号：US332391

申请日：1994-10-31

Applicant: Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

Inventor： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/34

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/0483

Abstract: A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

公开(公告)号：US5392238A

公开(公告)日：1995-02-21

申请号：US226474

申请日：1994-04-11

Applicant: Ryouhei Kirisawa

Inventor： Ryouhei Kirisawa

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: G11C16/0491 ,  G11C16/0483

Abstract: A semiconductor nonvolatile memory device according to the invention comprises a first cell block having with a current path and a plurality of memory cells, a second cell block having with a current path and a plurality of memory cells, the current path of the second cell block has an end connected to a corresponding end of the current path of the first cell block, a first line electrically connected to the other end of the current path of the first cell block, and a second line electrically connected to the other end of the current path of the second cell block. The first and second lines are made to operate a bit line and a source line, or vise versa, depending on which one of said cell blocks is selected for data retrieval.

Abstract translation: 根据本发明的半导体非易失性存储器件包括具有电流路径和多个存储单元的第一单元块，具有电流路径和多个存储单元的第二单元块，第二单元块的当前通路 具有连接到第一单元块的电流路径的对应端的端部，电连接到第一单元块的电流路径的另一端的第一线，以及电连接到电流的另一端的第二线 路径的第二个单元格块。 第一和第二行用于操作位线和源极线，或者反之亦然，取决于选择哪一个所述单元块用于数据检索。

公开(公告)号：US08598643B2

公开(公告)日：2013-12-03

申请号：US13235425

申请日：2011-09-18

Applicant: Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

Inventor： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

公开(公告)号：US08507972B2

公开(公告)日：2013-08-13

申请号：US12821551

申请日：2010-06-23

Applicant: Shigeto Oota ,  Yoshimasa Mikajiri ,  Masaru Kito ,  Ryouhei Kirisawa

Inventor： Shigeto Oota ,  Yoshimasa Mikajiri ,  Masaru Kito ,  Ryouhei Kirisawa

IPC: H01L29/94

CPC classification number: H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括层叠结构单元，半导体柱，存储层，内绝缘膜，外绝缘膜和帽绝缘膜。 该单元包括在多个电极间绝缘膜上沿第一方向交替堆叠的多个电极膜。 支柱沿第一方向刺穿层叠的结构单元。 存储层设置在电极膜和半导体柱之间。 内部绝缘膜设置在存储层和半导体柱之间。 外绝缘膜设置在存储层和电极膜之间。 帽绝缘膜设置在外绝缘膜和电极膜之间，并且帽绝缘膜具有比外绝缘膜更高的相对介电常数。

公开(公告)号：US08294191B2

公开(公告)日：2012-10-23

申请号：US12943349

申请日：2010-11-10

Applicant: Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

Inventor： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

IPC: H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。