公开(公告)号：US20060003595A1

公开(公告)日：2006-01-05

申请号：US10882482

申请日：2004-06-30

Applicant: Matthias Passlack ,  Nicholas Medendorp

Inventor： Matthias Passlack ,  Nicholas Medendorp

IPC: H01L21/469 ,  H01L21/31 ,  H01L21/4763 ,  H01L21/3205

CPC classification number: H01L21/3105 ,  H01L21/28264

Abstract: The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between about 230° C. and about 400° C. The semiconductor structure is exposed to an atmosphere that is supersaturated with water vapor or vapor of deuterium oxide. The exposure takes place at elevated temperature and continues for a period of time between about 5 minutes to about 120 minutes. It has been found that the method of the present invention results in a semiconductor product that has significantly improved performance characteristics over semiconductors that are not passivated, or that use a dry hydrogen method of passivation.

Abstract translation: 本发明提供一种钝化设置在III-V半导体衬底上的氧化物的方法。 该方法旨在用于栅极质量氧化物层中使用的电介质叠层，没食子酸酯化合物和镓化合物。 该方法包括在约230℃和约400℃之间的升高的温度下加热半导体结构。将半导体结构暴露于用水蒸气或氧化氘蒸汽过饱和的气氛中。 曝光在升高的温度下进行，并持续约5分钟至约120分钟之间的时间。 已经发现，本发明的方法产生了与不被钝化的半导体相比具有明显改善的性能特性的半导体产品，或者使用干法氢化钝化方法。

公开(公告)号：US06756320B2

公开(公告)日：2004-06-29

申请号：US10051494

申请日：2002-01-18

Applicant: Matthias Passlack ,  Nicholas William Medendorp, Jr.

Inventor： Matthias Passlack ,  Nicholas William Medendorp, Jr.

IPC: H01L2131

CPC classification number: H01L29/513 ,  C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02112 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/28194 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/31666 ,  H01L29/4232 ,  H01L29/511 ,  H01L29/517

Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga—Gd-oxide provides a low oxide leakage current density.

Abstract translation: 提供了一种化合物半导体结构，其包括具有其上将要形成介电材料的表面的GaAs基支撑半导体结构。 第一层氧化镓位于支撑半导体结构的表面上以与其形成界面。 在第一层上设置第二层Ga-Gd氧化物。 GaAs基支撑半导体结构可以是诸如至少部分完成的半导体器件（例如，金属氧化物场效应晶体管，异质结双极晶体管或半导体激光器）的基于GaAs的异质结构。 以这种方式，提供了在氧化物 - GaAs界面处具有低缺陷密度和低氧化物漏电流密度的电介质层结构，因为电介质结构由Ga 2 O 3层，然后由Ga-Gd-氧化物层形成 。 Ga 2 O 3层用于与GaAs基支持半导体结构形成高质量的界面，而Ga-Gd氧化物提供低的氧化物漏电流密度。

公开(公告)号：US6030453A

公开(公告)日：2000-02-29

申请号：US812950

申请日：1997-03-04

Applicant: Matthias Passlack ,  Jonathan K. Abrokwah ,  Ravi Droopad ,  Corey D. Overgaard

Inventor： Matthias Passlack ,  Jonathan K. Abrokwah ,  Ravi Droopad ,  Corey D. Overgaard

IPC: H01L21/205 ,  H01L21/02 ,  H01L21/31 ,  H01L21/316 ,  C30B23/02

CPC classification number: H01L21/31604

Abstract: A production process for protecting the surface of compound semiconductor wafers includes providing a multi-wafer epitaxial production system with a transfer and load module, a III-V growth chamber and an insulator chamber. The wafer is placed in the transfer and load module and the pressure is reduced to .ltoreq.10.sup.-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The wafer is then moved through the transfer and load module to the insulator chamber and an insulating cap layer is formed by thermally evaporating gallium oxide molecules from an effusion cell using an evaporation source in an oxide crucible, which oxide crucible does not form an eutectic alloy with the evaporation source

Abstract translation: 用于保护化合物半导体晶片的表面的制造方法包括提供具有传输和负载模块，III-V生长室和绝缘体室的多晶片外延生产系统。 将晶片放置在传送和加载模块中，并将压力降低到10-10托，之后将晶片移动到III-V生长室，并且将化合物半导体材料层外延生长在 晶圆。 然后将晶片通过传输和负载模块移动到绝缘体室，并且通过使用氧化物坩埚中的蒸发源从渗出电池热蒸发氧化镓分子而形成绝缘盖层，该氧化物坩埚不形成共晶合金 与蒸发源

公开(公告)号：US6025281A

公开(公告)日：2000-02-15

申请号：US993603

申请日：1997-12-18

Applicant: Matthias Passlack ,  Jonathan K. Abrokwah ,  Sandeep Pendharkar ,  Stephen B. Clemens ,  Jimmy Z. Yu ,  Brian Bowers

Inventor： Matthias Passlack ,  Jonathan K. Abrokwah ,  Sandeep Pendharkar ,  Stephen B. Clemens ,  Jimmy Z. Yu ,  Brian Bowers

IPC: H01L21/28 ,  H01L21/30 ,  H01L21/3105 ,  H01L21/316

CPC classification number: H01L21/28264 ,  H01L21/3006 ,  H01L21/3105

Abstract: A method of passivating interface states of oxide-compound semiconductor interfaces using molecular, atomic, or isotopic species wherein said species are applied before oxide deposition in ultra-high vacuum, or during interruption of oxide deposition in ultra-high vacuum (preferentially after oxide surface coverage of a submonolayer, a monolayer, or a few monolayers), or during oxide deposition in ultra-high vacuum, or after completion of oxide deposition, or before or after any processing steps of the as deposited interface structure. In a preferred embodiment, hydrogen or deuterium atoms are applied to a Ga.sub.2 O.sub.3 --GaAs interface at some point before, during, or after oxide deposition in ultra-high vacuum, or before or after any processing steps of the as deposited interface structure, at any given and useful substrate temperature wherein the atomic species can be provided by any one of RF discharge, microwave plasma discharge, or thermal dissociation.

Abstract translation: 使用分子，原子或同位素物质钝化氧化物 - 化合物半导体界面的界面状态的方法，其中所述物质在超高真空中的氧化物沉积之前或在超高真空（优选氧化物表面之后） 亚单层，单层或几个单层的覆盖），或者在超高真空中的氧化物沉积期间，或在氧化物沉积完成之后，或在作为沉积的界面结构的任何处理步骤之前或之后。 在一个优选的实施方案中，在超高真空中的氧化物沉积之前，期间或之后的某个时刻，或者在作为沉积的界面结构的任何处理步骤之前或之后，在任何时候，在任何时候，将氢或氘原子施加到Ga 2 O 3 -GaAs- 给定和有用的衬底温度，其中可以通过RF放电，微波等离子体放电或热解离中的任何一种来提供原子种类。

公开(公告)号：US5821171A

公开(公告)日：1998-10-13

申请号：US408678

申请日：1995-03-22

Applicant: Minghwei Hong ,  Jueinai Raynien Kwo ,  Joseph Petrus Mannaerts ,  Matthias Passlack ,  Fan Ren ,  George John Zydzik

Inventor： Minghwei Hong ,  Jueinai Raynien Kwo ,  Joseph Petrus Mannaerts ,  Matthias Passlack ,  Fan Ren ,  George John Zydzik

IPC: C23C14/08 ,  H01L29/51 ,  H01L31/04 ,  H01L33/44 ,  H01S5/00 ,  H01S5/028 ,  H01L21/316

CPC classification number: H01L29/517 ,  C23C14/08 ,  H01L33/44 ,  H01S5/028

Abstract: A high quality interface between a GaAs-based semiconductor and a Ga.sub.2 O.sub.3 dielectric an be formed if the semiconductor surface is caused to have less than 1% of a monolayer impurity coverage at completion of the first monolayer of the Ga.sub.2 O.sub.3 on the surface. This is achieved, for instance, by preparing the surface of a GaAs wafer under UHV conditions in a first growth chamber, transferring the wafer through a transfer module under UHV to a second growth chamber that is also under UHV, and growing the dielectric by evaporation of Ga.sub.2 O.sub.3 from a solid source, the process carried out such that the integrated impurity exposure of the surface is at most 100 Langmuirs. Articles according to the invention have low interface state density (

Abstract translation: 如果半导体表面在表面上的Ga 2 O 3的第一单层完成时具有小于单层杂质覆盖率的1％，则形成GaAs基半导体和Ga 2 O 3电介质之间的高质量界面。 这通过例如通过在第一生长室中在UHV条件下制备GaAs晶片的表面来实现，将晶片通过UHV下的转移模块转移到也在UHV下的第二生长室，并通过蒸发使电介质生长 的Ga 2 O 3来自固体源，所述方法进行，使得表面的综合杂质暴露量为至多100兰缪尔。 根据本发明的制品具有低界面态密度（<1011 / cm2×Ve）和界面复合速度（<104cm / s）。 根据本发明的半导体/ Ga 2 O 3结构可以有利地用于各种电子或光电子器件，例如GaAs基MOS-FET，HBT，太阳能电池上的激光器。

公开(公告)号：US08735903B2

公开(公告)日：2014-05-27

申请号：US12974775

申请日：2010-12-21

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L29/15

CPC classification number: H01L29/7783 ,  H01L21/823807 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/517 ,  H01L29/7781

Abstract: Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum EC1; a second semiconductor layer having a discrete hole level H0; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer; wherein the discrete hole level H0 is positioned below the conduction band minimum Ec1 for zero bias applied to the gate metal layer.

Abstract translation: 描述了用于状态密度（“DOS”）工程化FET的层结构。 一个实施例包括用于制造n沟道晶体管的层结构。 层结构包括具有导带最小EC1的第一半导体层; 具有离散孔级H0的第二半导体层; 布置在第一和第二半导体层之间的宽带隙半导体阻挡层; 设置在所述第一半导体层上方的栅介质层; 以及栅极金属层，其设置在所述栅极介电层的上方; 其中离散孔电平H0位于施加到栅极金属层的零偏压的导带最小值Ec1之下。

公开(公告)号：US20120056246A1

公开(公告)日：2012-03-08

申请号：US13293910

申请日：2011-11-10

Applicant: Jonathan K. Abrokwah ,  Ravindranath Droopad ,  Matthias Passlack

Inventor： Jonathan K. Abrokwah ,  Ravindranath Droopad ,  Matthias Passlack

IPC: H01L29/78

CPC classification number: H01L29/7783 ,  H01L23/3192 ,  H01L29/207 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Abstract translation: 通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。 在半导体层上形成介电层。 在电介质层上形成密封层并暴露于氧等离子体。 在源 - 漏电极之间的电介质层上形成栅电极。 电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。 希望在密封层的上方设置另外的例如氮化硅的密封层。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

公开(公告)号：US20110193092A1

公开(公告)日：2011-08-11

申请号：US12974954

申请日：2010-12-21

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L29/205

CPC classification number: H01L29/7787 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/088 ,  H01L27/092 ,  H01L29/122 ,  H01L29/155 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/517 ,  H01L29/7783 ,  H01L31/03046 ,  H01L31/035236 ,  H01L31/1844

Abstract: A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H0; a second semiconductor layer having a conduction band minimum EC2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H0 below the conduction band minimum Ec2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.

Abstract translation: 描述了一个单端晶体管器件。 在一个实施例中，n沟道晶体管包括具有离散孔级H0的第一半导体层; 具有导带最小EC2的第二半导体层; 布置在第一和第二半导体层之间的宽带隙半导体阻挡层; 设置在所述第一半导体层上方的栅介质层; 以及栅极金属层，其设置在所述栅极介电层上方并且具有选择的有效功函数以将所述离散孔电平H0定位在所述导带最小值Ec2以下，以将零偏压施加到所述栅极金属层并获得n端子特性。

公开(公告)号：US20110156051A1

公开(公告)日：2011-06-30

申请号：US13042948

申请日：2011-03-08

Applicant: Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

Inventor： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

IPC: H01L29/20 ,  H01L21/28 ,  H01L29/772

CPC classification number: H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract translation: 实施例包括具有低泄漏肖特基接触的半导体器件。 通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。 在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。 使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

公开(公告)号：US20110068368A1

公开(公告)日：2011-03-24

申请号：US12562852

申请日：2009-09-18

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L27/0207 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/8258 ,  H01L27/0605

Abstract: A semiconductor device comprising a honeycomb heteroepitaxy and method for making same are described. One embodiment is a method comprising defining a mask on a silicon substrate, the mask comprising a plurality of nano-size openings therethrough; subsequent to the defining, creating essentially defect-free non-silicon semiconductor nano-islands on portions of a surface of the silicon substrate exposed through the mask openings; subsequent to the creating, depositing high-k gate dielectric is deposited on the nano-islands; and subsequent to the deposition, constructing transistors on the nano-islands.

Abstract translation: 描述了包括蜂窝异质外延的半导体器件及其制造方法。 一个实施例是一种方法，包括在硅衬底上限定掩模，所述掩模包括穿过其中的多个纳米尺寸的开口; 在定义之后，在通过掩模开口暴露的硅衬底的表面的部分上产生基本上无缺陷的非硅半导体纳米岛; 在生成之后，沉积高k栅极电介质沉积在纳米岛上; 并且在沉积之后，在纳米岛上构建晶体管。