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公开(公告)号：US20060003595A1
公开(公告)日：2006-01-05
申请号：US10882482
申请日：2004-06-30
IPC分类号： H01L21/469 , H01L21/31 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/3105 , H01L21/28264
摘要： The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between about 230° C. and about 400° C. The semiconductor structure is exposed to an atmosphere that is supersaturated with water vapor or vapor of deuterium oxide. The exposure takes place at elevated temperature and continues for a period of time between about 5 minutes to about 120 minutes. It has been found that the method of the present invention results in a semiconductor product that has significantly improved performance characteristics over semiconductors that are not passivated, or that use a dry hydrogen method of passivation.
摘要翻译： 本发明提供一种钝化设置在III-V半导体衬底上的氧化物的方法。 该方法旨在用于栅极质量氧化物层中使用的电介质叠层，没食子酸酯化合物和镓化合物。 该方法包括在约230℃和约400℃之间的升高的温度下加热半导体结构。将半导体结构暴露于用水蒸气或氧化氘蒸汽过饱和的气氛中。 曝光在升高的温度下进行，并持续约5分钟至约120分钟之间的时间。 已经发现，本发明的方法产生了与不被钝化的半导体相比具有明显改善的性能特性的半导体产品，或者使用干法氢化钝化方法。
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公开(公告)号：US07202182B2
公开(公告)日：2007-04-10
申请号：US10882482
申请日：2004-06-30
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/3105 , H01L21/28264
摘要： The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between about 230° C. and about 400° C. The semiconductor structure is exposed to an atmosphere that is supersaturated with water vapor or vapor of deuterium oxide. The exposure takes place at elevated temperature and continues for a period of time between about 5 minutes to about 120 minutes. It has been found that the method of the present invention results in a semiconductor product that has significantly improved performance characteristics over semiconductors that are not passivated, or that use a dry hydrogen method of passivation.
摘要翻译： 本发明提供一种钝化设置在III-V半导体衬底上的氧化物的方法。 该方法旨在用于栅极质量氧化物层中使用的电介质叠层，没食子酸酯化合物和镓化合物。 该方法包括在约230℃和约400℃之间的升高的温度下加热半导体结构。将半导体结构暴露于用水蒸气或氧化氘蒸气过饱和的气氛中。 曝光在升高的温度下进行，并持续约5分钟至约120分钟之间的时间。 已经发现，本发明的方法产生了与不被钝化的半导体相比具有明显改善的性能特性的半导体产品，或者使用干法氢化钝化方法。
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3.发明申请公开(公告)号：US20050221623A1
公开(公告)日：2005-10-06
申请号：US11136845
申请日：2005-05-25
IPC分类号： C23C14/08 , C30B23/02 , C30B29/16 , H01L21/28 , H01L21/31 , H01L21/316 , H01L29/423 , H01L29/51
CPC分类号： H01L29/513 , C23C14/08 , C30B23/02 , C30B29/16 , H01L21/02112 , H01L21/02192 , H01L21/022 , H01L21/02269 , H01L21/28194 , H01L21/28264 , H01L21/31604 , H01L21/31666 , H01L29/4232 , H01L29/511 , H01L29/517
摘要： A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga—Gd-oxide provides a low oxide leakage current density.
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公开(公告)号：US06963090B2
公开(公告)日：2005-11-08
申请号：US10339379
申请日：2003-01-09
IPC分类号： H01L21/336 , H01L31/072
CPC分类号： H01L29/402 , H01L29/42376 , H01L29/517 , H01L29/66522 , H01L29/7784 , H01L29/7785
摘要： An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial material layer has a channel layer and at least one doped layer. A gate oxide layer overlies the epitaxial layer structure. The EMOSFET further includes a metal gate electrode overlying the gate oxide layer and source and drain ohmic contacts overlying the epitaxial layer structure.
摘要翻译： 提供无植入物的增强型金属氧化物半导体场效应晶体管（EMOSFET）。 EMOSFET具有III-V族化合物半导体衬底和覆盖III-V族化合物半导体衬底的外延层结构。 外延材料层具有沟道层和至少一个掺杂层。 栅极氧化层覆盖在外延层结构上。 EMOSFET还包括覆盖栅极氧化物层的金属栅极电极和覆盖外延层结构的源极和漏极欧姆触点。
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公开(公告)号：US09735239B2
公开(公告)日：2017-08-15
申请号：US13444695
申请日：2012-04-11
IPC分类号： H01L29/66 , H01L29/205 , H01L29/10 , H01L29/78
CPC分类号： H01L29/205 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.
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公开(公告)号：US20140021532A1
公开(公告)日：2014-01-23
申请号：US13553405
申请日：2012-07-19
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66977 , B82Y10/00 , H01L29/0657 , H01L29/0676 , H01L29/068 , H01L29/0688 , H01L29/1037 , H01L29/1054 , H01L29/205 , H01L29/42372 , H01L29/66356 , H01L29/66439 , H01L29/66522 , H01L29/66666 , H01L29/7391 , H01L29/775 , H01L29/7827
摘要： Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
摘要翻译： 除此之外，本文提供了用于形成垂直隧道场效应晶体管（FET）的一种或多种技术以及所产生的垂直隧道FET。 在一个实施例中，垂直隧道FET通过在第一类型的衬底区域上形成芯体形成，围绕围绕圆周的圆周形成第二类型沟道壳体，围绕围绕圆周的圆周形成栅极电介质，形成 围绕圆周大于芯圆周的栅电极，并且在第二类型沟槽壳体的一部分上形成第二类型区域，其中第二类型具有与第一类型的掺杂相反的掺杂。 以这种方式，能够进行线路隧道，从而为垂直隧道FET提供增强的隧道效率。
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公开(公告)号：US20130270607A1
公开(公告)日：2013-10-17
申请号：US13444695
申请日：2012-04-11
IPC分类号： H01L29/205 , H01L21/336 , H01L29/78
CPC分类号： H01L29/205 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.
摘要翻译： 公开了一种用于信道区域的系统和方法。 一个实施例包括具有多个双层的沟道区，包括交替的互补材料，例如InAs层和GaSb层。 互补材料的交替层为通道区域提供期望的带隙特性，整体上材料的各层可能不是。
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公开(公告)号：US20110193134A1
公开(公告)日：2011-08-11
申请号：US13009036
申请日：2011-01-19
申请人： Matthias Passlack
发明人： Matthias Passlack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/205 , H01L29/22 , H01L29/267
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer.
摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成缓冲层，该缓冲层包含第一化合物半导体，该第一化合物半导体包括元素周期表III-V族之一元素; 和II-VI族。 该方法包括在缓冲层上形成沟道层。 沟道层包含第二化合物半导体，其包括来自周期表的III-V族的元素。 该方法包括在沟道层上形成栅极。 该方法包括在栅极的任一侧上的沟道层的区域上沉积杂质。 该方法包括执行退火处理以激活沟道层中的杂质。
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9.发明申请THIN BODY MOSFET WITH CONDUCTING SURFACE CHANNEL EXTENSIONS AND GATE-CONTROLLED CHANNEL SIDEWALLS 审中-公开具有导通表面通道延伸和门控通道的薄体MOSFET公开(公告)号：US20110068348A1
公开(公告)日：2011-03-24
申请号：US12562790
申请日：2009-09-18
申请人： Matthias Passlack
发明人： Matthias Passlack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66522 , H01L29/512 , H01L29/7833
摘要： A thin body MOSFET with conducting surface channel extensions and gate-controlled channel sidewalls is described. One embodiment is a MOSFET comprising a semiconductor substrate; a channel layer disposed on a top surface of the substrate; a gate dielectric layer interposed between a gate electrode and the channel layer; and dielectric extension layers disposed on top of the channel layer and interposed between the gate electrode and Ohmic contacts. The gate dielectric layer comprises a first material, the first material forming an interface of low defectivity with the channel layer. In contrast, the dielectric extensions comprise a second material different than the first material, the second material forming a conducting surface channel with the channel layer.
摘要翻译： 描述了具有导电表面通道扩展和栅极控制通道侧壁的薄体MOSFET。 一个实施例是包括半导体衬底的MOSFET; 设置在所述基板的上表面上的沟道层; 插入在栅电极和沟道层之间的栅介质层; 以及设置在沟道层顶部并介于栅电极和欧姆接触之间的电介质延伸层。 栅介质层包括第一材料，第一材料形成具有低缺陷率的界面与沟道层。 相反，电介质延伸部包括不同于第一材料的第二材料，第二材料与沟道层形成导电表面沟道。
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公开(公告)号：US20090085073A1
公开(公告)日：2009-04-02
申请号：US11864274
申请日：2007-09-28
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28264 , H01L29/517
摘要： A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.
摘要翻译： 形成化合物半导体MOSFET结构的部分（10）的方法包括：形成化合物半导体层结构（14）和覆盖其上的氧化物层（20）。 形成化合物半导体结构（14）包括形成至少一个沟道材料（16）和覆盖至少一个沟道材料的III族富集表面终止层（18）。 形成氧化物层（20）包括形成氧化物层以覆盖III族富集表面终止层，并且包括（a）基本上一致地沉积（a（i））三元氧化物和（ （ii））比三元氧化物更复杂的氧化物和（b）使用（b（i））三元氧化物和（b（ii））中的至少一种沉积氧化物分子，其比 三元氧化物。
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