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    Method and system for a gallium nitride vertical JFET with self-aligned gate metallization
    32.
    发明授权
    Method and system for a gallium nitride vertical JFET with self-aligned gate metallization 有权
    具有自对准栅极金属化的氮化镓垂直JFET的方法和系统

    公开(公告)号：US08716078B2

    公开(公告)日：2014-05-06

    申请号：US13468325

    申请日：2012-05-10

    Applicant: Donald R. Disney ,  Richard J. Brown ,  Hui Nie

    Inventor： Donald R. Disney ,  Richard J. Brown ,  Hui Nie

    IPC: H01L21/337

    CPC classification number: H01L29/8083 ,  H01L29/2003 ,  H01L29/66909

    Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

    Abstract translation: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底并且包括漂移区，沟道区和延伸区的第一III族氮化物外延层。 沟道区域通过漂移区域与III族氮化物衬底分离。 通道区域的特征在于第一宽度。 延伸区域通过沟道区域与漂移区域分离。 延伸区域的特征在于小于第一宽度的第二宽度。 半导体器件还包括耦合到延伸区域的顶表面的第二III族氮化物外延层，耦合到沟道区域的侧壁并相对于延伸区域横向自对准的III族氮化物栅极结构，以及 栅极金属结构与III族氮化物栅极结构电接触并且相对于延伸区域横向自对准。

    Lateral high-voltage transistor and associated method for manufacturing
    33.
    发明授权
    Lateral high-voltage transistor and associated method for manufacturing 有权
    横向高压晶体管及其制造方法

    公开(公告)号：US08686503B2

    公开(公告)日：2014-04-01

    申请号：US13212097

    申请日：2011-08-17

    Applicant: Donald R. Disney ,  Ognjen Milic

    Inventor： Donald R. Disney ,  Ognjen Milic

    IPC: H01L29/66

    CPC classification number: H01L29/063 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    Abstract: The present disclosure discloses a lateral high-voltage transistor and associated method for making the same. The lateral high-voltage transistor comprises a semiconductor layer of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer separated from the source region; a first isolation layer atop the semiconductor layer between the source region and the drain region; a first well region of the second conductivity type surrounding the drain region, extending towards the source region and separated from the source region; a second well region of the first conductivity type surrounding the source region; a gate positioned atop the first isolation layer above the second well region and an adjacent portion of the first well region; and a first buried layer of the first conductivity type under the first well region adjacent to the source region side of the lateral high-voltage transistor. A JFET is formed using the gate as a JFET top gate and the first buried layer as a JFET bottom gate.

    Abstract translation: 本公开公开了一种横向高压晶体管及其制造方法。 横向高压晶体管包括第一导电类型的半导体层; 在半导体层中与第一导电类型相反的第二导电类型的源极区; 所述半导体层中的所述第二导电类型的漏极区域与所述源极区域分离; 在源极区域和漏极区域之间的半导体层顶部的第一隔离层; 围绕所述漏极区的所述第二导电类型的第一阱区，朝向所述源极区延伸并与所述源极区分离; 围绕源区的第一导电类型的第二阱区; 位于所述第二阱区域上方的所述第一隔离层顶部的栅极和所述第一阱区域的相邻部分; 以及与所述横向高压晶体管的源极侧相邻的所述第一阱区域之下的所述第一导电类型的第一掩埋层。 使用栅极作为JFET顶栅形成JFET，并且将第一掩埋层形成为JFET底栅。

    High-voltage devices with integrated over-voltage protection and associated methods
    35.
    发明授权
    High-voltage devices with integrated over-voltage protection and associated methods 有权
    具有集成过压保护和相关方法的高压器件

    公开(公告)号：US08670219B2

    公开(公告)日：2014-03-11

    申请号：US13162512

    申请日：2011-06-16

    Applicant: Donald R. Disney

    Inventor： Donald R. Disney

    IPC: H02H9/00 ,  H02H3/20 ,  H02H9/04

    CPC classification number: H03K17/0822

    Abstract: The present technology discloses a high-voltage device comprising a high-voltage transistor and an integrated over-voltage protection circuit. The over-voltage protection circuit monitors a voltage across the high-voltage transistor to detect an over-voltage condition of the high-voltage transistor, and turns the high-voltage transistor ON when the over-voltage condition is detected. Thus, once the high-voltage transistor is in over-voltage condition, the high-voltage transistor is turned ON and can dissipate the power from the over-voltage event through its channel.

    Abstract translation: 本技术公开了一种包括高压晶体管和集成过电压保护电路的高压装置。 过电压保护电路监视高电压晶体管两端的电压，以检测高电压晶体管的过压状态，并在检测到过电压状态时将高电压晶体管导通。 因此，一旦高电压晶体管处于过电压状态，高压晶体管导通，并可通过其通道从过电压事件中消耗功率。

    CMOS devices with reduced short channel effects
    36.
    发明授权
    CMOS devices with reduced short channel effects 有权
    具有减少短通道效应的CMOS器件

    公开(公告)号：US08664067B2

    公开(公告)日：2014-03-04

    申请号：US12949272

    申请日：2010-11-18

    Applicant: Donald R. Disney

    Inventor： Donald R. Disney

    IPC: H01L29/772 ,  H01L21/336

    CPC classification number: H01L29/7833 ,  H01L21/2652 ,  H01L29/1083 ,  H01L29/6659

    Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.

    Abstract translation: MOS晶体管包括选择性地增加身体区域的掺杂剂浓度的掺杂分布。 掺杂分布具有浅部分，其增加正好在栅极下的晶体管的表面下方的体区的掺杂剂浓度，以及增加源极和漏极区下的体区的掺杂剂浓度的深部。 可以通过在栅极，源极区和漏极区注入掺杂剂来形成掺杂分布。 掺杂剂可以通过掩模的开口在高能离子注入步骤中植入，掩模的开口也用于执行另一个注入步骤。 掺杂剂也可以通过专用掩模的开口植入。

    Electronic circuit control element with tap element
    38.
    发明授权
    Electronic circuit control element with tap element 失效
    带抽头元件的电子电路控制元件

    公开(公告)号：US08611108B2

    公开(公告)日：2013-12-17

    申请号：US13571209

    申请日：2012-08-09

    Applicant: Donald R. Disney

    Inventor： Donald R. Disney

    IPC: H02M3/335

    CPC classification number: H01L29/7803 ,  G05F1/14 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7802 ,  H01L29/7813 ,  H02M1/36 ,  H02M3/335 ,  H02M3/33507 ,  H02M3/33553 ,  H02M3/33561 ,  H02M2001/0009

    Abstract: An example control element for use in a power supply includes a high-voltage transistor and a control circuit to control switching of the high-voltage transistor. The high-voltage transistor includes a drain region, source region, tap region, drift region, and tap drift region, all of a first conductivity type. The transistor also includes a body region of a second conductivity type. An insulated gate is included in the transistor such that when the insulated gate is biased a channel is formed across the body region to form a conduction path between the source region and the drift region. A voltage at the tap region with respect to the source region is substantially constant and less than a voltage at the drain region with respect to the source region in response to the voltage at the drain region exceeding a pinch off voltage.

    Abstract translation: 用于电源的示例性控制元件包括高压晶体管和用于控制高压晶体管的开关的控制电路。 高压晶体管包括漏区，源区，抽头区，漂移区和抽头漂移区，全部为第一导电类型。 晶体管还包括第二导电类型的体区。 绝缘栅极包括在晶体管中，使得当绝缘栅极被偏置时，跨越体区域形成沟道以在源极区域和漂移区域之间形成传导路径。 相对于源极区域的抽头区域处的电压基本上是恒定的，并且响应于漏极区域处的电压超过夹断电压而小于相对于源极区域的漏极区域处的电压。

    Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same
    39.
    发明申请
    Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same 审中-公开
    具有掩埋层的横向高压晶体管及其制造方法

    公开(公告)号：US20130161740A1

    公开(公告)日：2013-06-27

    申请号：US13332862

    申请日：2011-12-21

    Applicant: Donald R. Disney ,  Ognjen Milic

    Inventor： Donald R. Disney ,  Ognjen Milic

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/0847 ,  H01L29/0634 ,  H01L29/405 ,  H01L29/66659 ,  H01L29/7835

    Abstract: A lateral high-voltage transistor comprising a semiconductor layer of a first conductivity type; a source region of a second conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer; a first isolation layer atop the semiconductor layer between the source and the drain regions; a first well region of the second conductivity type surrounding the drain region; a gate positioned atop the first isolation layer adjacent to the source region; a spiral resistive field plate atop the first isolation layer spiraling between the drain region and the gate, wherein the spiral resistive field plate is coupled in series to the source and drain regions; and a buried layer of the first conductivity type in the first well region, wherein the buried layer is buried beneath a top surface of the first well region below the spiral resistive field plate.

    Abstract translation: 一种横向高压晶体管，包括第一导电类型的半导体层; 半导体层中的第二导电类型的源极区; 半导体层中的第二导电类型的漏极区; 源极和漏极区域之间的半导体层顶部的第一隔离层; 围绕所述漏极区的所述第二导电类型的第一阱区; 位于与源区相邻的第一隔离层顶上的栅极; 在所述漏极区和所述栅极之间螺旋化的所述第一隔离层顶部的螺旋电阻场板，其中所述螺旋电阻场板串联耦合到所述源极和漏极区; 以及第一阱区域中的第一导电类型的掩埋层，其中所述掩埋层埋在所述螺旋电阻场板下方的所述第一阱区域的顶表面之下。

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