公开(公告)号：US20240387672A1

公开(公告)日：2024-11-21

申请号：US18786531

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/51 ,  H01L29/786

Abstract: Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US12148810B2

公开(公告)日：2024-11-19

申请号：US18154087

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Jo-Chun Hung ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

公开(公告)号：US20240379348A1

公开(公告)日：2024-11-14

申请号：US18781257

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/02 ,  C23C16/455 ,  H01L21/383 ,  H01L21/443 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.

公开(公告)号：US12142659B2

公开(公告)日：2024-11-12

申请号：US18358537

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer.

公开(公告)号：US20240363718A1

公开(公告)日：2024-10-31

申请号：US18767174

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28568 ,  H01L21/82345 ,  H01L29/401 ,  H01L29/785

Abstract: A method includes forming a gate dielectric layer on a semiconductor region, and depositing a first aluminum-containing work function layer using a first aluminum-containing precursor. The first aluminum-containing work function layer is over the gate dielectric layer. A second aluminum-containing work function layer is deposited using a second aluminum-containing precursor, which is different from the first aluminum-containing precursor. The second aluminum-containing work function layer is deposited over the first aluminum-containing work function layer. A conductive region is formed over the second aluminum-containing work function layer.

公开(公告)号：US20240363349A1

公开(公告)日：2024-10-31

申请号：US18771311

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/0338 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/66795

Abstract: Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.

公开(公告)号：US20240355882A1

公开(公告)日：2024-10-24

申请号：US18760656

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US12125706B2

公开(公告)日：2024-10-22

申请号：US18331387

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen Peng ,  Te-Yang Lai ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/02356 ,  H01L21/28158 ,  H01L21/3115 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions may be modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.

公开(公告)号：US20240332010A1

公开(公告)日：2024-10-03

申请号：US18738742

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen Peng ,  Te-Yang Lai ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02356 ,  H01L21/02181 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/76829 ,  H01L21/76871 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545

Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

公开(公告)号：US12087775B2

公开(公告)日：2024-09-10

申请号：US17464369

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui ,  Chieh-Ping Wang

IPC: H01L27/00 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02326 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.