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    Area-limited software utility
    21.
    发明授权
    Area-limited software utility 有权
    区域限制软件实用程序

    公开(公告)号：US09563576B1

    公开(公告)日：2017-02-07

    申请号：US11848833

    申请日：2007-08-31

    申请人： Daniel J. Horon

    发明人： Daniel J. Horon

    IPC分类号： G06F12/04 ,  G06F12/14 ,  G06F13/00

    CPC分类号： G06F21/6218 ,  G06F12/14 ,  G06F13/00 ,  G06F2221/2111 ,  G06F2221/2149

    摘要： Computers and networks are configured to operate according to alternative protocols for using software applications, depending on geographic location. In one approach each computer incorporates a GPS receiver using GPS satellite signals to generate the computer's current location. The location is compared with permitted use region information stored in the computer or network, e.g. based on a boundary defining a permitted use region. In another approach, E-911 compliant transceivers use signals from E-911 towers in the same manner. In a further approach, each computer incorporates a WiFi adaptor, RFID reader or RFID tag, and the territory is defined by the distance from a center point. In all cases, the computer either operates under a relatively open protocol relative to using a given software application, or operates under a relatively restricted protocol, depending on whether it is inside or outside of the permitted use region.

    摘要翻译： 根据地理位置，计算机和网络被配置为根据用于使用软件应用的替代协议进行操作。 在一种方法中，每台计算机结合使用GPS卫星信号的GPS接收器来产生计算机的当前位置。 将该位置与存储在计算机或网络中的允许使用区域信息进行比较，例如， 基于限定允许使用区域的边界。 在另一种方法中，E-911兼容收发器以相同的方式使用E-911塔的信号。 在另一种方法中，每个计算机包括WiFi适配器，RFID读取器或RFID标签，并且领域由距离中心点的距离限定。 在所有情况下，计算机相对于使用给定的软件应用在相对开放的协议下操作，或者在相对受限的协议下操作，这取决于它是在内部还是在允许的使用区域之外。

    COMMUNICATION BETWEEN INTEGRATED GRAPHICS PROCESSING UNITS
    22.
    发明申请
    COMMUNICATION BETWEEN INTEGRATED GRAPHICS PROCESSING UNITS 审中-公开
    集成图形处理单元之间的通信

    公开(公告)号：US20170018050A1

    公开(公告)日：2017-01-19

    申请号：US15121217

    申请日：2014-02-27

    申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    发明人： Indrajit Roy ,  Sangman Kim ,  Vanish Talwar

    IPC分类号： G06T1/20 ,  G06F15/167 ,  G06T1/60 ,  G06F12/1009 ,  G06F12/1036 ,  G06F9/50 ,  G06F12/04

    CPC分类号： G06T1/20 ,  G06F9/50 ,  G06F12/04 ,  G06F12/1009 ,  G06F12/1036 ,  G06F15/167 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/60

    摘要： The communication between integrated graphics processing units (CPUs) is disclosed. A first integrated GPU of a first computing device obtains a tuple pertaining to data to be transmitted to a second integrated CPU of a second computing device. The tuple comprises at least a length of the data. The first integrated GPU allocates a virtual address space to the data based on the length of the data, where the virtual address space has a plurality of virtual addresses. Further, a mapping table of a mapping between the plurality of virtual addresses and a plurality of bus addresses is provided by the first integrated GPU to a communication module of the first computing device to transmit the data, where the plurality of bus addresses indicate physical locations of the data.

    摘要翻译： 公开了集成图形处理单元（CPU）之间的通信。 第一计算设备的第一集成GPU获得与要发送到第二计算设备的第二集成CPU的数据相关的元组。 元组至少包括一段长度的数据。 第一集成GPU基于数据的长度为数据分配虚拟地址空间，其中虚拟地址空间具有多个虚拟地址。 此外，由第一集成GPU向第一计算设备的通信模块提供多个虚拟地址和多个总线地址之间的映射的映射表，以发送数据，其中多个总线地址指示物理位置 的数据。

    Multiple data channel memory module architecture
    23.
    发明授权
    Multiple data channel memory module architecture 有权

    公开(公告)号：US09449659B2

    公开(公告)日：2016-09-20

    申请号：US14673732

    申请日：2015-03-30

    申请人： Micron Technology, Inc.

    发明人： Tony M. Brewer ,  J. Michael Andrewartha ,  William D. O'Leary ,  Michael K. Dugan

    IPC分类号： G06F12/00 ,  G11C7/10 ,  G06F12/04 ,  G06F12/06

    CPC分类号： G06F12/0811 ,  G06F12/04 ,  G06F12/0607 ,  G06F2212/283 ,  G11C7/1072

    摘要： The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

    Apparatus and method for identifying similarity via dynamic decimation of token sequence n-grams
    27.
    发明授权
    Apparatus and method for identifying similarity via dynamic decimation of token sequence n-grams 有权
    通过令牌序列n-gram的动态抽取来识别相似度的装置和方法

    公开(公告)号：US09111095B2

    公开(公告)日：2015-08-18

    申请号：US14248622

    申请日：2014-04-09

    申请人： The Johns Hopkins University

    发明人： Jonathan D. Cohen

    IPC分类号： G06F11/00 ,  G06F12/04 ,  G06F12/16 ,  G06F7/04 ,  H04N7/16 ,  G06F21/56

    CPC分类号： G06F21/562 ,  G06F17/277 ,  G06F21/564

    摘要： An apparatus for identifying related code variants or text samples includes processing circuitry configured to execute instructions for receiving query binary code, processing the query binary code to generate one or more query code fingerprints comprising compressed representations of respective functional components of the query binary code, generating token sequence n-grams of the fingerprints, hashing the n-grams, partitioning samples by length to compare selected samples based on length, and identifying similarity via dynamic decimation of token sequence n-grams.

    摘要翻译： 用于识别相关代码变体或文本样本的装置包括处理电路，其被配置为执行用于接收查询二进制代码的指令，处理查询二进制代码以生成包括查询二进制代码的各个功能组件的压缩表示的一个或多个查询代码指纹， 令牌序列n-gram的指纹，散列n-gram，按长度分割样本以比较基于长度的选定样本，并通过令牌序列n-gram的动态抽取来识别相似度。

    Data writing method for writing updated data into rewritable non-volatile memory module, and memory controller, and memory storage apparatus using the same
    30.
    发明授权
    Data writing method for writing updated data into rewritable non-volatile memory module, and memory controller, and memory storage apparatus using the same 有权
    用于将更新的数据写入可重写非易失性存储器模块的数据写入方法，以及存储器控制器，以及使用其的存储器存储装置

    公开(公告)号：US09021218B2

    公开(公告)日：2015-04-28

    申请号：US14151841

    申请日：2014-01-10

    申请人： Phison Electronics Corp.

    发明人： Chih-Kang Yeh

    IPC分类号： G06F13/00 ,  G06F12/02 ,  G06F12/04

    CPC分类号： G06F12/0246 ,  G06F12/04 ,  G06F2212/7209

    摘要： A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened.

    摘要翻译： 提供了一种用于将更新的数据写入具有多个物理页面的闪存模块的方法，其中每个物理页面是闪存模块的最小写入单元。 该方法包括将物理页面划分为存储段并为每个存储段配置状态标记，其中状态标记指示存储在存储段中的数据的有效性。 该方法还包括将更新后的数据写入至少一个存储段并改变对应于包含更新数据的存储段的状态标记，其中对应于包含更新数据的存储段的状态标记表示有效状态，以及 对应于不包含更新数据的物理页面的其他存储段的状态标记表示无效状态。 从而有效地缩短将数据写入物理页面的时间。