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公开(公告)号：US10949347B2
公开(公告)日：2021-03-16
申请号：US16038571
申请日：2018-07-18
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/06 , G06F12/04 , G11C7/10
摘要： According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
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公开(公告)号：US11550719B2
公开(公告)日：2023-01-10
申请号：US17191542
申请日：2021-03-03
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/06 , G06F12/04 , G11C7/10
摘要： According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
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公开(公告)号：US09449659B2
公开(公告)日：2016-09-20
申请号：US14673732
申请日：2015-03-30
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.
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公开(公告)号：US10061699B2
公开(公告)日：2018-08-28
申请号：US15806217
申请日：2017-11-07
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/04 , G06F12/06 , G11C7/10
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
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公开(公告)号：US09824010B2
公开(公告)日：2017-11-21
申请号：US15254975
申请日：2016-09-01
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/04 , G06F12/06 , G11C7/10
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
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公开(公告)号：US20160371185A1
公开(公告)日：2016-12-22
申请号：US15254975
申请日：2016-09-01
IPC分类号： G06F12/0811
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
摘要翻译： 根据本公开的一个示例，系统包括被配置为提供对存储器访问操作的请求的计算元件和包括多个存储器，多个独立数据通道的存储器模块，每个独立数据通道耦合到 所述多个存储器，多个内部地址/控制信道，耦合到所述多个存储器中的一个的独立地址/控制信道中的每一个以及耦合到所述多个内部地址/控制信道并被配置为接收和解码的控制逻辑 用于存储器访问操作的地址和控制信息，所述控制逻辑还被配置为基于所接收的地址，针对所选择的独立数据信道选择性地将解码的地址和控制信息提供给所选择的内部地址/控制信道 以及用于存储器访问操作的控制信息。
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公开(公告)号：US20180060234A1
公开(公告)日：2018-03-01
申请号：US15806217
申请日：2017-11-07
IPC分类号： G06F12/0811 , G06F12/06 , G11C7/10 , G06F12/04
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
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