公开(公告)号：US20240282357A1

公开(公告)日：2024-08-22

申请号：US18598237

申请日：2024-03-07

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/00 ,  Y02D30/50

摘要： An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20240281019A1

公开(公告)日：2024-08-22

申请号：US18170100

申请日：2023-02-16

申请人： Rohde & Schwarz GmbH & Co. KG

发明人： Florian Galler ,  Julius Seeger

IPC分类号： G06F1/02 ,  G06F1/03 ,  G06F1/08

CPC分类号： G06F1/022 ,  G06F1/0328 ,  G06F1/08

摘要： The measurement circuit includes a clock input, a frequency converter circuit, and a first signal generator circuit. The clock input is configured to receive a reference clock signal. The first signal generator circuit includes a first clock generator circuit configured to generate a first clock signal having an adaptable frequency based on the reference clock signal. The first signal generator circuit further includes a first direct digital synthesizer (DDS) circuit configured to generate a local oscillator (LO) signal based on the first clock signal and based on an adaptable frequency tuning word (FTW) of the first DDS circuit. The adaptable frequency of the first clock signal and the adaptable FTW of the first DDS circuit are configured such that an IF signal is free of spurs emitted by the first DDS circuit at least in a predetermined frequency band.

公开(公告)号：US12067384B2

公开(公告)日：2024-08-20

申请号：US17827139

申请日：2022-05-27

申请人： Vizio, Inc.

发明人： W. Leo Hoarty

IPC分类号： G06F8/65 ,  G06F1/08 ,  G06F1/12

CPC分类号： G06F8/65 ,  G06F1/08 ,  G06F1/12

摘要： Systems and methods for updating firmware in an audio device, such as a soundbar, operatively connected to a Smart TV, are shown and described. Firmware update data is transmitted to the audio device via an audio return channel (ARC) of an HDMI cable. In certain of the systems, the firmware update data is transmitted to the audio device when no audio is being transmitted to or played by the audio device. In other systems, the firmware update data and real-time audio data are multiplexed by the Smart TV and are sent to the audio device via the audio return channel for subsequent demultiplexing and playback of the audio.

公开(公告)号：US20240275369A1

公开(公告)日：2024-08-15

申请号：US18647662

申请日：2024-04-26

申请人： Apple Inc.

发明人： Helena Deirdre O'SHEA ,  Dmitry CHERNIAVSKY ,  Tim SCHOENAUER ,  Ali MOAZ ,  Rahmi HEZAR ,  Ram KANUMALLI

IPC分类号： H03K5/1252 ,  G06F1/08 ,  G06F13/40

CPC分类号： H03K5/1252 ,  G06F1/08 ,  G06F13/4027

摘要： Embodiments relate to updating spur cancellation at a victim integrated circuit (IC) in accordance with dynamic changes in the operating frequencies of an aggressor IC. The aggressor IC changes its operating frequencies at an update time that is determined in advance. The update time and the changes to the operating frequencies are shared with the victim IC. The victim IC dynamically updates the relationships between frequencies of local clock signals for the victim IC and the aggressor IC. The victim IC generates a spur cancellation parameter based on the updated relationships of local clock frequencies, the update time and the changes to the operating frequencies of the aggressor IC, and configures a spur cancellation circuit. In this way, the victim IC may perform effective spur cancellation despite changes in the operating frequencies of the aggressor IC and deviation of the local clock frequencies.

公开(公告)号：US20240264628A1

公开(公告)日：2024-08-08

申请号：US18637461

申请日：2024-04-17

申请人： Samsung Display Co., Ltd.

发明人： SE-BYUNG CHAE

IPC分类号： G06F1/12 ,  G06F1/08 ,  G09G3/32 ,  G09G3/3225

CPC分类号： G06F1/12 ,  G06F1/08 ,  G09G3/32 ,  G09G3/3225 ,  G09G2310/08

摘要： A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

公开(公告)号：US20240264625A1

公开(公告)日：2024-08-08

申请号：US18164590

申请日：2023-02-05

申请人： NVIDIA Corp.

发明人： Jiale Liang ,  Tezaswi Raja ,  Suhas Satheesh ,  Shalimar Rasheed ,  Gaurav Ajwani ,  Ram Kumar Ranjith Kumar ,  Miloni Mehta

IPC分类号： G06F1/08 ,  H03K5/01

CPC分类号： G06F1/08 ,  H03K5/01 ,  H03K2005/00019

摘要： Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.

公开(公告)号：US12038780B1

公开(公告)日：2024-07-16

申请号：US18172185

申请日：2023-02-21

申请人： Synopsys, Inc.

发明人： Edoardo Contini ,  Giacomino Bollati ,  Alberto Minuti ,  Choon Haw Leong

IPC分类号： G06F1/08 ,  G04F10/00 ,  H03K5/01 ,  H03K17/687 ,  H03K5/00

CPC分类号： G06F1/08 ,  G04F10/005 ,  H03K5/01 ,  H03K17/6872 ,  H03K2005/00286

摘要： A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple clock periods of the multiphase clock system.

公开(公告)号：US20240223168A1

公开(公告)日：2024-07-04

申请号：US18148845

申请日：2022-12-30

申请人： Texas Instruments Incorporated

发明人： Tolga Dinc ,  Sachin Kalia ,  Swaminathan Sankaran

IPC分类号： H03K5/00 ,  G06F1/08 ,  H03H7/01

CPC分类号： H03K5/00006 ,  G06F1/08 ,  H03H7/0115 ,  H03H7/0161

摘要： Described embodiments include a circuit having a quadrature phase generator circuit having differential generator inputs, in-phase differential generator outputs and quadrature-phase differential generator outputs. A first frequency multiplier circuit has first differential multiplier inputs and a first multiplier output, wherein the first differential multiplier inputs are coupled to the in-phase differential generator outputs. A second frequency multiplier circuit has second differential multiplier inputs and a second multiplier output. The second multiplier differential inputs are coupled to the quadrature-phase differential generator outputs. A transformer includes a primary inductor and a secondary inductor, wherein the primary inductor is coupled between the first and second multiplier outputs, and the second inductor is coupled between an output voltage terminal and a ground terminal.

公开(公告)号：US20240220438A1

公开(公告)日：2024-07-04

申请号：US18090254

申请日：2022-12-28

申请人： Advanced Micro Devices, Inc.

发明人： Gabriel Hsiuwei Loh ,  Todd David Basso

IPC分类号： G06F13/40 ,  G06F1/08 ,  H01L23/538 ,  H01L25/065

CPC分类号： G06F13/4068 ,  G06F1/08 ,  H01L23/538 ,  H01L25/0655

摘要： The disclosed semiconductor package includes a first chiplet area for receiving a first chiplet, a second chiplet area for receiving a second chiplet, and a host die coupled to the first and second chiplet areas. The semiconductor package also includes an interconnect directly coupling the first chiplet area to the second chiplet area. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240219954A1

公开(公告)日：2024-07-04

申请号：US18439593

申请日：2024-02-12

申请人： FMAD Engineering (SNG) Pte. Ltd.

发明人： Aaron Foo

IPC分类号： G06F1/08 ,  G06F1/14

CPC分类号： G06F1/08 ,  G06F1/14

摘要： An embodiment may involve receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator; reading the local time value and writing it to a memory as a current time value; determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock; based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and modifying the local time increment by the adjustment.