公开(公告)号：US20250124848A1

公开(公告)日：2025-04-17

申请号：US19002741

申请日：2024-12-27

Applicant: Samsung Display Co., Ltd.

Inventor： HYUNCHANG KIM ,  SE-BYUNG CHAE

IPC: G09G3/20 ,  G05F1/46

Abstract: A power voltage generator includes an analog reference voltage generator configured to generate an analog reference voltage based on a first input voltage, a resistance string configured to generate distribution voltages by performing voltage distribution on the analog reference voltage, a decoding unit configured to generate reference voltages by decoding the distribution voltages, and a regulator unit configured to generate driving voltages based on the reference voltages.

公开(公告)号：US20240264628A1

公开(公告)日：2024-08-08

申请号：US18637461

申请日：2024-04-17

Applicant: Samsung Display Co., Ltd.

Inventor： SE-BYUNG CHAE

IPC: G06F1/12 ,  G06F1/08 ,  G09G3/32 ,  G09G3/3225

CPC classification number: G06F1/12 ,  G06F1/08 ,  G09G3/32 ,  G09G3/3225 ,  G09G2310/08

Abstract: A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

公开(公告)号：US20240194163A1

公开(公告)日：2024-06-13

申请号：US18369210

申请日：2023-09-18

Applicant: Samsung Display Co., Ltd.

Inventor： HYUNCHANG KIM ,  SE-BYUNG CHAE ,  SUBIN KIM ,  Sangmin Lee

IPC: G09G3/36 ,  G09G3/32 ,  G09G3/3258 ,  G09G3/3291

CPC classification number: G09G3/3696 ,  G09G3/32 ,  G09G3/3258 ,  G09G3/3291 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0276

Abstract: A gamma voltage control circuit includes a first amplifier and a second amplifier. The first amplifier is configured to generate a first primitive reference voltage based on a panel power voltage applied to a display panel. The second amplifier is configured to generate a first reference voltage based on the first primitive reference voltage, the panel power voltage and an internal power voltage.

公开(公告)号：US20230282174A1

公开(公告)日：2023-09-07

申请号：US17992325

申请日：2022-11-22

Applicant: Samsung Display Co., Ltd.

Inventor： HYUNCHANG KIM ,  SUBIN KIM ,  SE-BYUNG CHAE

IPC: G09G3/3291

CPC classification number: G09G3/3291 ,  G09G2310/027 ,  G09G2320/0626 ,  G09G2320/0242

Abstract: A display device may include a display panel which includes pixels, a data driver which provides data voltages corresponding to output image data to the pixels, and a data converter which generates a compensation grayscale from reference compensation values for compensating at least one selected from a color shift and a luminance shift corresponding to a temperature based on an input temperature, an input grayscale included in input image data, and an input luminance, and converts the input image data into the output image data based on the compensation grayscale.

公开(公告)号：US20230133606A1

公开(公告)日：2023-05-04

申请号：US17869200

申请日：2022-07-20

Applicant: Samsung Display Co., Ltd.

Inventor： SUBIN KIM ,  SE-BYUNG CHAE ,  HYUNCHANG KIM

IPC: G09G3/20 ,  G09G3/3275 ,  G09G3/3266 ,  G09G3/00

Abstract: Disclosed is a display device, which includes a display panel, a controller that receives an image signal and an external synchronization signal and generates a control signal, and a driver that generates a driving signal in response the control signal and provides the driving signal to the display panel. The controller includes a synchronization signal generator that generates an internal synchronization signal based on a reference clock signal, a corrector that corrects the internal synchronization signal to generate a corrected synchronization signal, and a control signal generator that generates the control signal, and the control signal generator generates the control signal based on the external synchronization signal when the external synchronization signal is in a normal state, and generates the control signal based on the internal synchronization signal when the external synchronization signal is in an abnormal state.

公开(公告)号：US20230123934A1

公开(公告)日：2023-04-20

申请号：US17969581

申请日：2022-10-19

Applicant: Samsung Display Co., Ltd.

Inventor： SE-BYUNG CHAE

IPC: G06F1/12 ,  G06F1/08 ,  G09G3/32 ,  G09G3/3225

Abstract: A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

公开(公告)号：US20220327985A1

公开(公告)日：2022-10-13

申请号：US17558998

申请日：2021-12-22

Applicant: Samsung Display Co., Ltd.

Inventor： SUBIN KIM ,  SEONGKYUN KIM ,  SE-BYUNG CHAE

IPC: G09G3/20

Abstract: A display apparatus includes a display panel, a data analyzer, a logic core and a latch. The display panel is configured to display an image. The data analyzer is configured to analyze input image data. The logic core is configured to compensate all of line data, compensate a part of the line data, or not compensate all of the line data according to an analysis result of the data analyzer. The latch is configured to receive compensated data from the logic core.

公开(公告)号：US20250124847A1

公开(公告)日：2025-04-17

申请号：US18988910

申请日：2024-12-20

Applicant: Samsung Display Co., Ltd.

Inventor： SUBIN KIM ,  SEONGKYUN KIM ,  SE-BYUNG CHAE

IPC: G09G3/20

Abstract: A display apparatus includes a display panel, a data analyzer, a logic core and a latch. The display panel is configured to display an image. The data analyzer is configured to analyze input image data. The logic core is configured to compensate all of line data, compensate a part of the line data, or not compensate all of the line data according to an analysis result of the data analyzer. The latch is configured to receive compensated data from the logic core.

公开(公告)号：US20250069542A1

公开(公告)日：2025-02-27

申请号：US18943914

申请日：2024-11-12

Applicant: Samsung Display Co., Ltd.

Inventor： SUBIN KIM ,  SE-BYUNG CHAE ,  HYUNCHANG KIM

IPC: G09G3/20 ,  G09G3/00 ,  G09G3/3266 ,  G09G3/3275

Abstract: Disclosed is a display device, which includes a display panel, a controller that receives an image signal and an external synchronization signal and generates a control signal, and a driver that generates a driving signal in response the control signal and provides the driving signal to the display panel. The controller includes a synchronization signal generator that generates an internal synchronization signal based on a reference clock signal, a corrector that corrects the internal synchronization signal to generate a corrected synchronization signal, and a control signal generator that generates the control signal, and the control signal generator generates the control signal based on the external synchronization signal when the external synchronization signal is in a normal state, and generates the control signal based on the internal synchronization signal when the external synchronization signal is in an abnormal state.

公开(公告)号：US20230419888A1

公开(公告)日：2023-12-28

申请号：US18463935

申请日：2023-09-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SE-BYUNG CHAE

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0275 ,  G09G2310/0267 ,  G09G2330/028 ,  G09G2300/0842 ,  G09G2330/021

Abstract: Disclosed is a data driving circuit including a noise filter, first through third voltage generators, and an output circuit. The noise filter receives a driving voltage and removes noise from the driving voltage to output a filtered driving voltage. The first voltage generator outputs a first voltage, a second voltage, and a third voltage. The second voltage generator generates a first reference voltage based on the filtered driving voltage, the first voltage, and the second voltage. The third voltage generator generates a second reference voltage based on the filtered driving voltage, the second voltage, and the third voltage. The output circuit outputs a data signal of a voltage level corresponding to an image signal based on the first reference voltage and the second reference voltage.