公开(公告)号：US12038780B1

公开(公告)日：2024-07-16

申请号：US18172185

申请日：2023-02-21

申请人： Synopsys, Inc.

发明人： Edoardo Contini ,  Giacomino Bollati ,  Alberto Minuti ,  Choon Haw Leong

IPC分类号： G06F1/08 ,  G04F10/00 ,  H03K5/01 ,  H03K17/687 ,  H03K5/00

CPC分类号： G06F1/08 ,  G04F10/005 ,  H03K5/01 ,  H03K17/6872 ,  H03K2005/00286

摘要： A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple clock periods of the multiphase clock system.