DYNAMIC CONFIGURATION OF SPUR CANCELLATION
    1.
    发明公开

    公开(公告)号:US20240275369A1

    公开(公告)日:2024-08-15

    申请号:US18647662

    申请日:2024-04-26

    Applicant: Apple Inc.

    CPC classification number: H03K5/1252 G06F1/08 G06F13/4027

    Abstract: Embodiments relate to updating spur cancellation at a victim integrated circuit (IC) in accordance with dynamic changes in the operating frequencies of an aggressor IC. The aggressor IC changes its operating frequencies at an update time that is determined in advance. The update time and the changes to the operating frequencies are shared with the victim IC. The victim IC dynamically updates the relationships between frequencies of local clock signals for the victim IC and the aggressor IC. The victim IC generates a spur cancellation parameter based on the updated relationships of local clock frequencies, the update time and the changes to the operating frequencies of the aggressor IC, and configures a spur cancellation circuit. In this way, the victim IC may perform effective spur cancellation despite changes in the operating frequencies of the aggressor IC and deviation of the local clock frequencies.

    SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS

    公开(公告)号:US20240097937A1

    公开(公告)日:2024-03-21

    申请号:US18515468

    申请日:2023-11-21

    Applicant: Apple Inc.

    Abstract: Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

    Configuration of Aggressor Integrated Circuit to Prevent Spur Interference at Victim Integrated Circuit

    公开(公告)号:US20240056066A1

    公开(公告)日:2024-02-15

    申请号:US18456364

    申请日:2023-08-25

    Applicant: Apple Inc.

    CPC classification number: H03K5/1252 G06F21/71

    Abstract: Embodiments relate to identifying frequencies to be protected at a victim integrated circuit (IC) and sending protection information including the identified frequencies to an aggressor IC. The aggressor IC configures its subsystems or circuits to operate using operating frequencies that prevents spurs that may interfere with the frequencies identified in the protection information. If not all of the frequencies in the protection information can be protected, the aggressor IC selects a subset of the frequencies to be protected. Then, the aggressor IC configures the operating frequencies of its subsystems or circuits so that spurs that they generate do not interfere with the selected frequencies.

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