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公开(公告)号：US20240313097A1
公开(公告)日：2024-09-19
申请号：US18513740
申请日：2023-11-20
发明人： JUNGGIL YANG , TAEHYUN KIM , TAEWON HA
IPC分类号： H01L29/775 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66
CPC分类号： H01L29/775 , H01L29/0673 , H01L29/0847 , H01L29/41733 , H01L29/42392 , H01L29/45 , H01L29/66439 , H01L29/66545 , H01L29/66553
摘要： Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a first region and a second region; an active region on the first region and a peripheral active region on the second region; a channel pattern on the active region; a peripheral channel pattern on the peripheral active region; a first gate electrode on the channel pattern; and a second gate electrode on the peripheral channel pattern. A linewidth of the second gate electrode is larger than a linewidth of the first gate electrode, and a difference in height between the first and second gate electrodes is smaller than about 10 nm, and a top surface of the second gate electrode has a doubly-concave shape.
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公开(公告)号：US20240313077A1
公开(公告)日：2024-09-19
申请号：US18537536
申请日：2023-12-12
发明人： Chulsung KIM , Yeonghan GWON , Jinkyung SON , Jaepo LIM
IPC分类号： H01L29/423 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/775
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/0847 , H01L29/41733 , H01L29/66439 , H01L29/775
摘要： Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a capping pattern on a top surface of the outer electrode. A line-width of the outer electrode is a first width. The outer electrode has a first height. The first height is equal to or less than the first width.
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公开(公告)号：US20240304241A1
公开(公告)日：2024-09-12
申请号：US18181054
申请日：2023-03-09
IPC分类号： G11C11/419 , H01L23/528 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786 , H10B10/00
CPC分类号： G11C11/419 , H01L23/5283 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/78696 , H10B10/125
摘要： An apparatus and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses pairs of transistors that are vertically stacked gate all around (GAA) transistors with gate terminals forming a T-shape with respect to one another and a single gate contact that overlaps only one active layer of the two active layers of the pair. Transistors of such a pair of field effect transistors (FETs) are referred to as TFETs. With respect to one another, the active layers of TFETs use opposite doping polarities and conduct current in an orthogonal direction. A non-overlapping distance between top and bottom active layers of a pair of TFETs is at least a width of a drain/source contact. The orthogonal current flow of the top and bottom active layers simplifies local connections that reduces the resistance and capacitance of the signal routes.
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公开(公告)号：US12087775B2
公开(公告)日：2024-09-10
申请号：US17464369
申请日：2021-09-01
发明人： Ting-Gang Chen , Bo-Cyuan Lu , Tai-Chun Huang , Chi On Chui , Chieh-Ping Wang
IPC分类号： H01L27/00 , H01L21/02 , H01L21/764 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L27/0924 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/0259 , H01L21/764 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L29/0665 , H01L29/41733 , H01L29/41791 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/7851 , H01L29/78696
摘要： A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.
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公开(公告)号：US12087669B1
公开(公告)日：2024-09-10
申请号：US18543111
申请日：2023-12-18
发明人： Jaehong Lee , Sooyoung Park , Wonhyuk Hong , Kang-Ill Seo
IPC分类号： H01L21/00 , H01L21/8238 , H01L23/48 , H01L27/07 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/481 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L27/0727 , H01L27/092 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Integrated circuit devices and methods of forming the same. As an example, an integrated circuit device may include a substrate; a first transistor structure on the substrate; a second transistor structure stacked in a vertical direction on the first transistor structure; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; and a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the substrate. The discharging path may extend through the isolation layer.
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公开(公告)号：US20240297228A1
公开(公告)日：2024-09-05
申请号：US18323587
申请日：2023-05-25
发明人： Wei-Yip Loh , Hong-Mao Lee , Harry Chien , Chih-Wei Chang
IPC分类号： H01L29/417 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H01L29/41733 , H01L21/823814 , H01L21/823821 , H01L27/0924 , H01L29/0673 , H01L29/41791 , H01L29/42392 , H01L29/495 , H01L29/4975 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： Semiconductor structures and methods of forming the same are provided. A method of the present disclosure includes receiving a workpiece that includes a bottom source/drain feature over a substrate, a first dielectric layer over the bottom source/drain feature, a top source/drain feature over the first dielectric layer, and a second dielectric layer over the top source/drain feature, forming a frontside opening through the second dielectric layer to expose a portion of the top source/drain feature, selectively depositing a first silicide layer on the exposed portion of the top source/drain feature, forming a top metal fill layer over the first silicide layer to fill the frontside opening, forming a backside opening through the substrate to expose a portion of the bottom source/drain feature, selectively depositing a second silicide layer on the exposed portion of the bottom source/drain feature, and forming a bottom metal fill layer on the second silicide layer.
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公开(公告)号：US20240290690A1
公开(公告)日：2024-08-29
申请号：US18220432
申请日：2023-07-11
发明人： Panjae PARK , Kang-ill SEO
IPC分类号： H01L23/48 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号： H01L23/481 , H01L29/0673 , H01L29/41733 , H01L29/41775 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： Provided is a semiconductor device in which a large-CPP area includes a 1st source/drain structure; a 1st frontside contact structure, at a front side of the semiconductor device, connected to the 1st source/drain structure; a 1st via structure, at a lateral side of the 1st source/drain structure, connected to the 1st frontside contact structure; a 2nd via structure on the 1st frontside via structure; a 1st frontside metal line, at the front side of the semiconductor device, connected to the 2nd via structure; and a 1st backside metal line, at a back side of the semiconductor device, connected to the 1st via structure.
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28.发明授权公开(公告)号：US12074219B2
公开(公告)日：2024-08-27
申请号：US17523076
申请日：2021-11-10
发明人： Yong-Jie Wu , Yen-Chung Ho , Hui-Hsien Wei , Chia-Jung Yu , Pin-Cheng Hsu , Feng-Cheng Yang , Chung-Te Lin
IPC分类号： H01L29/786 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/786 , H01L29/41733 , H01L29/42384 , H01L29/45 , H01L29/4908
摘要： A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.
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公开(公告)号：US12074204B2
公开(公告)日：2024-08-27
申请号：US17384667
申请日：2021-07-23
发明人： Jung-Hung Chang , Lo Heng Chang , Zhi-Chang Lin , Shih-Cheng Chen , Chien-Ning Yao , Kuo-Cheng Chiang , Chih-Hao Wang
IPC分类号： H01L29/417 , H01L21/8234 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/41733 , H01L21/823475 , H01L29/401 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/775 , H01L29/78606 , H01L29/0653 , H01L29/0665 , H01L29/0673 , H01L29/78696
摘要： A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.
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公开(公告)号：US12074061B2
公开(公告)日：2024-08-27
申请号：US17407083
申请日：2021-08-19
IPC分类号： H01L21/768 , H01L23/522 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L21/76846 , H01L23/5226 , H01L29/401 , H01L29/41733 , H01L29/42392 , H01L29/66742 , H01L29/78696
摘要： A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
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