公开(公告)号：US10002960B2

公开(公告)日：2018-06-19

申请号：US15436905

申请日：2017-02-20

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Meng Zhao

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167

CPC分类号： H01L29/7816 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the drift region. A gate structure is formed on a portion of each of the body region, the drift region, and the shallow trench isolation structure. A drain region is formed in the drift region on one side of the gate structure. A source region is formed in the body region on an other side of the gate structure. A first shallow doped region is formed in the drain region and the drift region to surround the shallow trench isolation structure.

公开(公告)号：US20180166322A1

公开(公告)日：2018-06-14

申请号：US15872747

申请日：2018-01-16

申请人： MagnaChip Semiconductor, Ltd.

发明人： Da Soon LEE ,  Hyung Suk CHOI ,  Jeong Gyu PARK ,  Gil Ho LEE ,  Hyun Tae JUNG ,  Meng An JUNG ,  Woo Sig MIN ,  Pil Seung KANG

IPC分类号： H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/764 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L21/76229 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.

公开(公告)号：US09985093B2

公开(公告)日：2018-05-29

申请号：US15439550

申请日：2017-02-22

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Yasuhiro Kagawa ,  Akihiko Furukawa ,  Shiro Hino ,  Hiroshi Watanabe ,  Masayuki Imaizumi

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/063 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/6631 ,  H01L29/66348 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

摘要： There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode 7 embedded into a trench 5 penetrating a base region 3. The gate electrode 7 is disposed into a lattice shape in a planar view, and a protective diffusion layer 13 is formed in a drift layer 2a at the portion underlying thereof. At least one of blocks divided by the gate electrode 7 is a protective contact region 20 on which the trench 5 is entirely formed. A protective contact 21 for connecting the protective diffusion layer 13 at a bottom portion of the trench 5 and a source electrode 9 is disposed on the protective contact region 20.

公开(公告)号：US20180097108A1

公开(公告)日：2018-04-05

申请号：US15285213

申请日：2016-10-04

申请人： Vanguard International Semiconductor Corporation

发明人： Wen-Hsin LIN ,  Yu-Hao HO ,  Shin-Cheng LIN

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/1045 ,  H01L29/42368

摘要： An ultra-high voltage device is provided. The ultra-high voltage device includes a substrate, a first well zone formed in the substrate, a second well zone having a surface formed in the substrate adjacent to the first well zone, a gate oxide formed on the first well zone and the second well zone of the substrate, a gate formed on the gate oxide, a channel formed in the first well zone underneath the gate oxide, an accumulation region formed in the second well zone underneath the gate oxide adjacent to the channel, wherein only a part of the accumulation region is implanted with a dopant to form an implant region therein, and an insulation region formed on the surface of the second well zone of the substrate adjacent to the accumulation region, wherein a boundary is formed between the insulation region and the accumulation region.

公开(公告)号：US09923556B2

公开(公告)日：2018-03-20

申请号：US15182558

申请日：2016-06-14

申请人： MaxPower Semiconductor Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng

IPC分类号： H01L29/78 ,  H03K17/041 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/78624 ,  H03K17/04106

摘要： Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

公开(公告)号：US09922865B2

公开(公告)日：2018-03-20

申请号：US14067335

申请日：2013-10-30

申请人： MagnaChip Semiconductor, Ltd.

发明人： Da Soon Lee ,  Hyung Suk Choi ,  Jeong Gyu Park ,  Gil Ho Lee ,  Hyun Tae Jung ,  Meng An Jung ,  Woo Sig Min ,  Pil Seung Kang

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/762 ,  H01L21/764 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/76229 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.

公开(公告)号：US09905687B1

公开(公告)日：2018-02-27

申请号：US15435694

申请日：2017-02-17

申请人： NXP USA, INC.

发明人： Ronghua Zhu ,  Xin Lin ,  Jiang-Kai Zuo

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/7816 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7833 ,  H01L29/7835

摘要： Laterally diffused metal-oxide-semiconductor (LDMOS) device is disclosed. The device is surrounded by an isolation ring and a buried layer of a first doping type, that is of the same type as its source and drain regions of the same doping type. A control gate of the device includes step gate dielectric.

公开(公告)号：US09887288B2

公开(公告)日：2018-02-06

申请号：US14957223

申请日：2015-12-02

申请人： Texas Instruments Incorporated

发明人： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L21/265 ,  H01L21/324

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

公开(公告)号：US09876095B2

公开(公告)日：2018-01-23

申请号：US15056993

申请日：2016-02-29

申请人： ams AG

发明人： Georg Roehrer

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/266 ,  H01L29/10

CPC分类号： H01L29/66681 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： An isolation area (10) is provided over a drift region (12) with a spacing (d) to a contact area (4) provided for a drain connection (D). The isolation area is used as an implantation mask, in order to produce a dopant profile of the drift region in which the dopant concentration increases toward the drain. The implantation of the dopant can be performed instead before the production of the isolation area, and the later production of the isolation area (10) changes the dopant profile also in a way that the dopant concentration increases toward the drain.

公开(公告)号：US09876071B2

公开(公告)日：2018-01-23

申请号：US14634801

申请日：2015-02-28

申请人： Texas Instruments Incorporated

发明人： Yongxi Zhang ,  Philip L Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P Pendharkar

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

CPC分类号： H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.