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公开(公告)号：US20240079046A1
公开(公告)日：2024-03-07
申请号：US18387204
申请日：2023-11-06
发明人： Jianquan Jia , Ying Cui , Kaikai You
IPC分类号： G11C11/408 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C11/419
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4094 , G11C11/4099 , G11C11/419
摘要： A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.
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公开(公告)号：US11864379B2
公开(公告)日：2024-01-02
申请号：US17568639
申请日：2022-01-04
发明人： Xuezhun Xie , Yali Song , Lei Jin , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia
CPC分类号： H10B41/27 , G11C5/025 , G11C16/0483 , G11C16/3436 , H10B43/27
摘要： The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage. The first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion.
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公开(公告)号：US20230326536A1
公开(公告)日：2023-10-12
申请号：US18203980
申请日：2023-05-31
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24
摘要： A three-dimensional (3D) memory device includes a first set of word lines coupled to first memory cells, a second set of word lines coupled to second memory cells, an interface dummy word line between the first and send sets of word lines, and a peripheral circuit coupled to the first and send memory cells. The peripheral circuit is configured to apply a first voltage to the interface dummy word line in a first pre-charge period when programming a first selected memory cell in the first memory cells, and apply a second voltage lower than the first voltage to the interface dummy word line in a second pre-charge period when programming a second selected memory cell in the second memory cells. Programing the first selected memory cell is earlier than the second selected memory cell.
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公开(公告)号：US20230307040A1
公开(公告)日：2023-09-28
申请号：US18204266
申请日：2023-05-31
发明人： Ying Cui , Jianquan Jia , Kaikai You
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/24 , H10B41/27
摘要： A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.
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25.发明授权公开(公告)号：US11626170B2
公开(公告)日：2023-04-11
申请号：US17187651
申请日：2021-02-26
发明人： Yali Song , Jianquan Jia , Kaikai You , An Zhang , XiangNan Zhao , Ying Cui , Shan Li , Kaiwei Li , Lei Jin , Xueqing Huang , Meng Lou , Jinlong Zhang
IPC分类号： G11C16/04 , G11C16/34 , H01L27/11556 , H01L27/11582
摘要： A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.
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公开(公告)号：US20220359022A1
公开(公告)日：2022-11-10
申请号：US17871472
申请日：2022-07-22
发明人： Yali Song , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia , Kaikai You
摘要： A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.
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公开(公告)号：US20220165741A1
公开(公告)日：2022-05-26
申请号：US17568639
申请日：2022-01-04
发明人： Xuezhun Xie , Yali Song , Lei Jin , Xiangnan Zhao , Yuanyuan Min , Jianquan Jia
IPC分类号： H01L27/11556 , G11C5/02 , G11C16/04 , H01L27/11582 , G11C16/34
摘要： The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage. The first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion.
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公开(公告)号：US11205494B2
公开(公告)日：2021-12-21
申请号：US17179356
申请日：2021-02-18
发明人： Jianquan Jia , Kaikai You , Ying Cui , Kaiwei Li , Yali Song , Shan Li , An Zhang
摘要： A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.
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公开(公告)号：US20210335426A1
公开(公告)日：2021-10-28
申请号：US16905880
申请日：2020-06-18
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
摘要： A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage; and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.
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公开(公告)号：US11158380B1
公开(公告)日：2021-10-26
申请号：US16905880
申请日：2020-06-18
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
摘要： A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage; and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.
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