公开(公告)号：US20190214296A1

公开(公告)日：2019-07-11

申请号：US16354362

申请日：2019-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Shuen-Shin Liang ,  Jung-Hao Chang ,  Chia-Hung Chu ,  Keng-Chu Lin

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76883

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

公开(公告)号：US20190103304A1

公开(公告)日：2019-04-04

申请号：US16103988

申请日：2018-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L21/762 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US09589856B2

公开(公告)日：2017-03-07

申请号：US14949206

申请日：2015-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Abstract translation: 一种方法包括蚀刻晶片上的低k电介质层以在低k电介质层中形成开口。 测量晶片中有害物质的量以获得测量结果。 响应于测量结果确定用于烘烤晶片的工艺条件。 使用确定的工艺条件烘烤晶片。

公开(公告)号：US20160190286A1

公开(公告)日：2016-06-30

申请号：US14586313

申请日：2014-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Cheng Wang ,  Chien-Feng Lin ,  Jeng-Yang Pan ,  Keng-Chu Lin

IPC: H01L29/66 ,  H01L21/30 ,  H01L29/34 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3003 ,  H01L29/165

Abstract: The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin.

Abstract translation: 本公开提供了根据一些实施例的形成半导体器件的方法。 该方法包括接收具有通过衬底突出的翅片的衬底，其中，鳍由第一半导体材料形成，在包括氢自由基的环境中暴露衬底，由此使用氢自由基钝化突出翅片，并外延生长帽 第二半导体材料的层以覆盖突出的翅片。

公开(公告)号：US20150041964A1

公开(公告)日：2015-02-12

申请号：US14523707

申请日：2014-10-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Yun Peng ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Hui-Chun Yang

IPC: H01L23/532 ,  H01L23/00

CPC classification number: H01L23/5329 ,  C23C16/401 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/7682 ,  H01L23/562 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.

Abstract translation: 多孔SiCOH的低k电介质层的方法和装置。 一种方法包括将半导体衬底放置在气相沉积室中; 将反应性气体引入气相沉积室以形成包含SiCOH和可分解致孔剂的电介质膜; 沉积介电膜以使Si-CH3与SiO网络键的比例小于或等于0.25; 并进行固化固化时间以从电介质膜基本上除去所有致孔剂。 在一个实施方案中，致孔剂包含环状烃。 造孔剂可以是UV固化的。 在实施例中，公开了用于沉积电介质膜的不同降低的Si-CH 3与SiO网络比。 公开了一种包括低k电介质层的半导体器件的装置。

公开(公告)号：US12094947B2

公开(公告)日：2024-09-17

申请号：US17384022

申请日：2021-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hung-Yu Yen ,  Ko-Feng Chen ,  Keng-Chu Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate, wherein the isolation structure includes a first dielectric layer in contact with the semiconductor substrate and a second dielectric layer over the first dielectric layer, wherein the first dielectric layer is between the second dielectric layer and the semiconductor substrate, the first dielectric layer comprises a bottom portion and a sidewall portion, and a thickness of the bottom portion is greater than a thickness of the sidewall portion.

公开(公告)号：US20240282761A1

公开(公告)日：2024-08-22

申请号：US18112853

申请日：2023-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Zheng Yong Liang ,  Wei-Ting Yeh ,  Jyh-Cherng Sheu ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L25/18 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L25/18 ,  H01L21/02016 ,  H01L21/02186 ,  H01L21/0231 ,  H01L21/02334 ,  H01L21/76822 ,  H01L23/5226

Abstract: A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.

公开(公告)号：US20230178593A1

公开(公告)日：2023-06-08

申请号：US17833273

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Ting Yeh ,  Hung-Yu Yen ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/02362 ,  H01L21/762 ,  H01L29/66545 ,  H01L29/66742

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

公开(公告)号：US11257753B2

公开(公告)日：2022-02-22

申请号：US16884925

申请日：2020-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Khaderbad Mrunal Abhijith ,  Yu-Yun Peng ,  Fu-Ting Yen ,  Chen-Han Wang ,  Tsu-Hsiu Perng ,  Keng-Chu Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.

公开(公告)号：US10510580B2

公开(公告)日：2019-12-17

申请号：US16103988

申请日：2018-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.