公开(公告)号：US11069558B2

公开(公告)日：2021-07-20

申请号：US16713981

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US20200013622A1

公开(公告)日：2020-01-09

申请号：US16576296

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yasutoshi Okuno ,  Teng-Chun Tsai ,  Ziwei Fang ,  Fu-Ting Yen

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

公开(公告)号：US10515809B2

公开(公告)日：2019-12-24

申请号：US16025708

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yasutoshi Okuno ,  Teng-Chun Tsai ,  Ziwei Fang ,  Fu-Ting Yen

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

公开(公告)号：US20190103304A1

公开(公告)日：2019-04-04

申请号：US16103988

申请日：2018-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L21/762 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US11637062B2

公开(公告)日：2023-04-25

申请号：US17676719

申请日：2022-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Khaderbad Mrunal Abhijith ,  Yu-Yun Peng ,  Fu-Ting Yen ,  Chen-Han Wang ,  Tsu-Hsiu Perng ,  Keng-Chu Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

公开(公告)号：US12283618B2

公开(公告)日：2025-04-22

申请号：US17716192

申请日：2022-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fu-Ting Yen ,  Kuei-Lin Chan ,  Yu-Yun Peng

IPC: H01L29/423 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.

公开(公告)号：US11296225B2

公开(公告)日：2022-04-05

申请号：US16421744

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Hao Yeh ,  Fu-Ting Yen

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/324

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.

公开(公告)号：US10964542B2

公开(公告)日：2021-03-30

申请号：US16576296

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yasutoshi Okuno ,  Teng-Chun Tsai ,  Ziwei Fang ,  Fu-Ting Yen

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.

公开(公告)号：US20200006565A1

公开(公告)日：2020-01-02

申请号：US16421744

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Hao Yeh ,  Fu-Ting Yen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/762

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.

公开(公告)号：US11257753B2

公开(公告)日：2022-02-22

申请号：US16884925

申请日：2020-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Khaderbad Mrunal Abhijith ,  Yu-Yun Peng ,  Fu-Ting Yen ,  Chen-Han Wang ,  Tsu-Hsiu Perng ,  Keng-Chu Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.