公开(公告)号：US20220238672A1

公开(公告)日：2022-07-28

申请号：US17578981

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Suhyeong LEE

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11582

Abstract: A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

公开(公告)号：US20220077321A1

公开(公告)日：2022-03-10

申请号：US17370480

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Minhyun LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/76 ,  H01L21/02 ,  H01L29/66

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

公开(公告)号：US20190148493A1

公开(公告)日：2019-05-16

申请号：US16248945

申请日：2019-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Haeryong KIM ,  Hyeonjin SHIN ,  Seunggeol NAM ,  Seongjun PARK

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L29/04 ,  H01L29/267

CPC classification number: H01L29/0847 ,  H01L21/28512 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

公开(公告)号：US20160343805A1

公开(公告)日：2016-11-24

申请号：US15010807

申请日：2016-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Haeryong KIM ,  Hyeonjin SHIN ,  Seunggeol NAM ,  Seongjun PARK

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L29/165 ,  H01L29/78 ,  H01L29/267

CPC classification number: H01L29/0847 ,  H01L21/28512 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

Abstract translation: 半导体器件包括半导体层，与半导体层电接触的金属层和半导体层与金属层之间的二维材料层并具有二维晶体结构。

公开(公告)号：US20150364589A1

公开(公告)日：2015-12-17

申请号：US14533802

申请日：2014-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho LEE ,  Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE

IPC: H01L29/775 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/1606 ,  H01L21/187 ,  H01L21/28512 ,  H01L23/485 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/7781 ,  H01L29/7839 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a graphene-metal bonding structure, a method of manufacturing the graphene-metal bonding structure, and a semiconductor device including the graphene-metal bonding structure. According to example embodiments, a graphene-metal bonding structure includes: a graphene layer; a metal layer on the graphene layer; and an intermediate material layer between the graphene layer and the metal layer. The intermediate material layer forms an edge-contact with the metal layer from boundary portions of a material contained in the intermediate material layer that contact the metal layer.

Abstract translation: 提供了石墨烯 - 金属结合结构，石墨烯 - 金属结合结构的制造方法以及包括石墨烯 - 金属结合结构的半导体器件。 根据示例性实施例，石墨烯 - 金属结合结构包括：石墨烯层; 石墨烯层上的金属层; 以及石墨烯层和金属层之间的中间材料层。 中间材料层与包含在与金属层接触的中间材料层中的材料的边界部分与金属层形成边缘接触。

公开(公告)号：US20250066950A1

公开(公告)日：2025-02-27

申请号：US18942936

申请日：2024-11-11

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Seokmo HONG ,  Minhyun LEE ,  Seunggeol NAM ,  Kyungyeol MA

IPC: C30B29/38 ,  H01L21/02

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US20240363689A1

公开(公告)日：2024-10-31

申请号：US18761779

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L21/02568 ,  H01L29/408 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20230197811A1

公开(公告)日：2023-06-22

申请号：US18171502

申请日：2023-02-20

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun LEE ,  Minsu SEOL ,  Ho Won JANG ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/66439

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

公开(公告)号：US20230189673A1

公开(公告)日：2023-06-15

申请号：US18167354

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun LEE ,  Houk JANG ,  Donhee HAM ,  Chengye LIU ,  Henry Julian HINTON ,  Haeryong KIM ,  Hyeonjin SHIN

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/8836 ,  H10B63/84 ,  H10N70/011 ,  H10N70/841 ,  H10N70/8845

Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

公开(公告)号：US20230155017A1

公开(公告)日：2023-05-18

申请号：US18157478

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7788 ,  H01L27/092 ,  H01L29/24 ,  H01L29/7831 ,  H01L29/78642 ,  H01L29/41741

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.