公开(公告)号：US12266659B2

公开(公告)日：2025-04-01

申请号：US17843263

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunhwi Cho ,  Jinkyu Kim ,  Myunggil Kang ,  Dongwon Kim ,  Jaechul Kim ,  Sanghoon Lee

IPC: H01L27/118 ,  H03K19/20

Abstract: A semiconductor device includes a substrate including a first device region and a second device region, active regions spaced apart from each other on the substrate, having a constant width, extending in a first direction parallel to an upper surface of the substrate and including a first active region and a second active region provided on the first device region and a third active region and a fourth active region provided on the second device region, a plurality of channel layers provided on the active regions and configured to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate, gate structures provided on the substrate and extending to cross the active regions and the plurality of channel layers, and source/drain regions provided on the active regions on at least one side of the gate structures.

公开(公告)号：US12261208B2

公开(公告)日：2025-03-25

申请号：US18538575

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghee Park ,  Myunggil Kang ,  Uihui Kwon ,  Seungkyu Kim ,  Ahyoung Kim ,  Youngseok Song

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

公开(公告)号：US12211942B2

公开(公告)日：2025-01-28

申请号：US17398504

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojin Jeong ,  Myunggil Kang ,  Junggil Yang ,  Junbeom Park

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.

公开(公告)号：US20240322012A1

公开(公告)日：2024-09-26

申请号：US18602274

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeonghee Son ,  Myunggil Kang ,  Dongwon Kim ,  Jongsu Kim ,  Changwoo Noh ,  Beomjin Park

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including an active region extending in a first horizontal direction, a nanosheet stack apart from the active region, a plurality of gate structures extending in a second horizontal direction and including a plurality of gate electrodes, a plurality of source/drain regions arranged on sidewalls of the gate structures, and a device isolation layer extending in a vertical direction, wherein the plurality of gate structures include a first gate structure in which a source/drain region is arranged on one sidewall and the device isolation layer is arranged on the other sidewall, and a second gate structure in which source/drain regions are arranged on both sidewalls, wherein the plurality of gate electrodes of the first gate structure include a main gate electrode positioned at the uppermost end and a plurality of sub-gate electrodes, and an internal spacer is between the device isolation layer and the plurality of sub-gate electrodes.

公开(公告)号：US20240321956A1

公开(公告)日：2024-09-26

申请号：US18614804

申请日：2024-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosuk Choi ,  Beomjin Park ,  Myunggil Kang ,  Dongwon Kim ,  Hyumin Yoo ,  Soojin Jeong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region that protrudes from a substrate and extends in a first horizontal direction, a plurality of nanosheets disposed on the fin-type active region and separated from each other in the vertical direction, a gate line that extends in a second horizontal direction and that surrounds the plurality of nanosheets on the fin-type active region, and includes respective sub-gate portions between the plurality of nanosheets and a main gate portion above the uppermost layer of the plurality of nanosheets, a source/drain region disposed on the fin-type active region, adjacent to the gate line, and connected to the plurality of nanosheets, and a plurality of inner spacers interposed between the gate line and the source/drain region. The shapes of first inner spacers that face the sub-gate portions differ from the shape of a second inner spacer that faces the main gate portion.

公开(公告)号：US11955475B2

公开(公告)日：2024-04-09

申请号：US18148810

申请日：2022-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woocheol Shin ,  Myunggil Kang ,  Minyi Kim ,  Sanghoon Lee

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L21/823481

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

公开(公告)号：US11728388B2

公开(公告)日：2023-08-15

申请号：US17694994

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunhwi Cho ,  Byounghak Hong ,  Myunggil Kang

IPC: H01L29/161 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/161 ,  H01L29/1041 ,  H01L29/7848

Abstract: A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.

公开(公告)号：US20220344463A1

公开(公告)日：2022-10-27

申请号：US17719996

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hakchul Jung ,  Myunggil Kang ,  Jungho Do ,  Sanghoon Baek

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L23/48

Abstract: An integrated circuit may include a first cell and a second cell. The first cell includes a first transistor in which nanosheets included in a first nanosheet stack and a second nanosheet stack extend in a first direction to pass through a first gate electrode that extends in a second direction intersecting with the first direction. The second cell includes a second transistor in which one or more nanosheets included in a third nanosheet stack extends in the first direction to pass through a second gate electrode that extends in the second direction. A length of the first cell in the second direction may be greater than a length of the second cell in the second direction.

公开(公告)号：US11217695B2

公开(公告)日：2022-01-04

申请号：US16815744

申请日：2020-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Lee ,  Krishna Bhuwalka ,  Myunggil Kang ,  Kyoungmin Choi

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).