公开(公告)号：US20160020205A1

公开(公告)日：2016-01-21

申请号：US14674123

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/04 ,  H01L29/423 ,  H01L49/02 ,  H01L29/16

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/78

Abstract: Provided is a semiconductor device including a substrate, first and second gate structures provided on the substrate, a source/drain region provided adjacent to the first gate structure, an interlayered insulating layer provided on the substrate to cover the source/drain region and the first and second gate structures, a source/drain contact hole penetrating the interlayered insulating layer and exposing the source/drain region, a trench formed in the interlayered insulating layer to expose a top surface of the second gate structure, a source/drain contact plug provided in the source/drain contact hole to be in contact with the source/drain region, and a resistor pattern provided in the trench to be in contact with a top surface of the second gate structure.

Abstract translation: 提供了一种半导体器件，其包括衬底，设置在衬底上的第一和第二栅极结构，与第一栅极结构相邻设置的源极/漏极区域，设置在衬底上以覆盖源极/漏极区域的第一层间绝缘层和第一 以及第二栅极结构，穿过所述层间绝缘层并暴露所述源极/漏极区域的源极/漏极接触孔，形成在所述层间绝缘层中以暴露所述第二栅极结构的顶表面的沟槽，提供的源极/漏极接触插塞 在源极/漏极接触孔中与源极/漏极区域接触，以及设置在沟槽中以与第二栅极结构的顶表面接触的电阻器图案。

公开(公告)号：US09184293B2

公开(公告)日：2015-11-10

申请号：US14454943

申请日：2014-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Un Kim ,  Hyun-Seung Song ,  Dong-Hyun Kim

IPC: H01L27/20 ,  H01L29/78 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7851 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/66803

Abstract: Methods of fabricating semiconductor devices are provided including providing a substrate having a first region and a second region, the substrate defining trenches in the first and second regions; forming active fins on the first and second regions, the active fins protruding from the trenches in the first and second regions; forming spacers on sidewalls of the active fins in the first and second regions; recessing floors of the trenches under the spacers to provide extensions of the active fins; implanting impurities of a first type in the extensions of the active fins in the first region; and implanting impurities of a second, type, different from the first type, in the extensions of the active fins in the second region.

Abstract translation: 提供制造半导体器件的方法包括提供具有第一区域和第二区域的衬底，所述衬底限定第一和第二区域中的沟槽; 在所述第一和第二区域上形成活动翅片，所述活动翅片从所述第一和第二区域中的沟槽突出; 在所述第一和第二区域中的活动翅片的侧壁上形成间隔物; 在间隔物下方的沟槽的凹陷地板，以提供活动鳍片的延伸; 将第一类型的杂质植入第一区域中活性鳍片的延伸部分; 以及将第二类型的不同于第一类型的杂质植入第二区域中的活性鳍片的延伸部分。

公开(公告)号：US12249648B2

公开(公告)日：2025-03-11

申请号：US17857608

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Seung Song ,  Hyo-Jin Kim ,  Kyoung-Mi Park ,  Hwi-Chan Jun ,  Seung-Seok Ha

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

公开(公告)号：US20230011401A1

公开(公告)日：2023-01-12

申请号：US17932851

申请日：2022-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US11482602B2

公开(公告)日：2022-10-25

申请号：US17034088

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

公开(公告)号：US10916534B2

公开(公告)日：2021-02-09

申请号：US16395691

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Seok Ha ,  Kyoung-Mi Park ,  Hyun-Seung Song ,  Keon Yong Cheon ,  Dae Won Ha

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.

公开(公告)号：US09640529B2

公开(公告)日：2017-05-02

申请号：US15196781

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hwi-Chan Jun

IPC: H01L27/06 ,  H01L21/285 ,  H01L49/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/51

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53266 ,  H01L23/535 ,  H01L28/24 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

公开(公告)号：US09356018B2

公开(公告)日：2016-05-31

申请号：US14674123

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song

IPC: H01L27/11 ,  H01L27/06 ,  H01L49/02 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/78

Abstract: Provided is a semiconductor device including a substrate, first and second gate structures provided on the substrate, a source/drain region provided adjacent to the first gate structure, an interlayered insulating layer provided on the substrate to cover the source/drain region and the first and second gate structures, a source/drain contact hole penetrating the interlayered insulating layer and exposing the source/drain region, a trench formed in the interlayered insulating layer to expose a top surface of the second gate structure, a source/drain contact plug provided in the source/drain contact hole to be in contact with the source/drain region, and a resistor pattern provided in the trench to be in contact with a top surface of the second gate structure.

Abstract translation: 提供了一种半导体器件，其包括衬底，设置在衬底上的第一和第二栅极结构，与第一栅极结构相邻设置的源极/漏极区域，设置在衬底上以覆盖源极/漏极区域的第一层间绝缘层和第一 以及第二栅极结构，穿过所述层间绝缘层并暴露所述源极/漏极区域的源极/漏极接触孔，形成在所述层间绝缘层中以暴露所述第二栅极结构的顶表面的沟槽，提供的源极/漏极接触插塞 在源极/漏极接触孔中与源极/漏极区域接触，以及设置在沟槽中以与第二栅极结构的顶表面接触的电阻器图案。

公开(公告)号：US08835252B2

公开(公告)日：2014-09-16

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。