公开(公告)号：US10691859B2

公开(公告)日：2020-06-23

申请号：US15908291

申请日：2018-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Woo Seo ,  Ha-Young Kim ,  Hyun-Jeong Roh

IPC: G06F30/392 ,  G03F1/70 ,  H01L21/311 ,  G03F7/20 ,  G06F30/00 ,  G06F30/39 ,  G06F119/18

Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

公开(公告)号：US10429443B2

公开(公告)日：2019-10-01

申请号：US15663852

申请日：2017-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Sung-Wee Cho ,  Dal-Hee Lee ,  Jae-Ha Lee

IPC: G01R31/3185 ,  H03K3/3562

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

公开(公告)号：US10411677B2

公开(公告)日：2019-09-10

申请号：US15649776

申请日：2017-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Dalhee Lee ,  Hyoung-Suk Oh ,  Keunho Lee ,  Taejoong Song ,  Sungwe Cho

IPC: H03K3/356 ,  H03K23/00 ,  H03K3/3562

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

公开(公告)号：US10332798B2

公开(公告)日：2019-06-25

申请号：US15624039

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  JinTae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC: H01L21/8238 ,  H01L27/06 ,  G06F17/50 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/02

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

公开(公告)号：US10242984B2

公开(公告)日：2019-03-26

申请号：US15614911

申请日：2017-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Sutae Kim ,  Donghyun Kim ,  Ha-Young Kim ,  Jung-ho Do ,  Sunyoung Park ,  Sanghoon Baek ,  Jaewan Choi

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

公开(公告)号：US09946828B2

公开(公告)日：2018-04-17

申请号：US14926128

申请日：2015-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Tae Kim ,  Ha-Young Kim ,  Jae-Woo Seo

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: A method of designing a layout of an integrated circuit (IC), which is implemented by a computer system or a processor, includes receiving input layout data, and performing a design rule check with regard to a plurality of patterns. The method includes, merging, from among a first pattern and a second pattern against the design rule, the first pattern with a third pattern connected to a same net as the first pattern, and generating output layout data.

公开(公告)号：US09887210B2

公开(公告)日：2018-02-06

申请号：US15238912

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

IPC: H01L21/76 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/8238 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US09698056B2

公开(公告)日：2017-07-04

申请号：US15094764

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Jin Tae Kim ,  Jae-Woo Seo ,  Dong-yeon Heo

IPC: H01L27/06 ,  H01L21/768 ,  G06F17/50 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L21/823475 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629

Abstract: A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.