公开(公告)号：US11574193B2

公开(公告)日：2023-02-07

申请号：US16122789

申请日：2018-09-05

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan M. Hatcher

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/04

Abstract: A method and system for training a neural network are described. The method includes providing at least one continuously differentiable model of the neural network. The at least one continuously differentiable model is specific to hardware of the neural network. The method also includes iteratively training the neural network using the at least one continuously differentiable model to provide at least one output for the neural network. Each iteration uses at least one output of a previous iteration and a current continuously differentiable model of the at least one continuously differentiable model.

公开(公告)号：US11461620B2

公开(公告)日：2022-10-04

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US20200234881A1

公开(公告)日：2020-07-23

申请号：US16417346

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Palle

IPC: H01G4/12 ,  H01L29/51 ,  H01L29/78

Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

公开(公告)号：US20190131977A1

公开(公告)日：2019-05-02

申请号：US15886179

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H03K19/21 ,  H03K19/18 ,  G06N3/063

Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

公开(公告)号：US09893187B2

公开(公告)日：2018-02-13

申请号：US15342008

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Chris Bowen ,  Kiyotaka Imai ,  Mark S. Rodder

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

公开(公告)号：US09831323B2

公开(公告)日：2017-11-28

申请号：US15267134

申请日：2016-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Robert Christopher Bowen ,  Borna J. Obradovic ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/201 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/04 ,  H01L21/465

CPC classification number: H01L29/6681 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02485 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/7853

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

公开(公告)号：US20170338346A1

公开(公告)日：2017-11-23

申请号：US15342003

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

公开(公告)号：US20170271477A1

公开(公告)日：2017-09-21

申请号：US15340827

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66553 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

公开(公告)号：US09768062B1

公开(公告)日：2017-09-19

申请号：US15276748

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  David Seo ,  Kota Oikawa ,  Kim Changhwa ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/785

Abstract: A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

公开(公告)号：US09525053B2

公开(公告)日：2016-12-20

申请号：US14304008

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Mark S. Rodder ,  Robert C. Bowen ,  Jorge A. Kittl

IPC: H01L29/04 ,  H01L29/778 ,  H01L29/12 ,  H01L29/78 ,  H01L29/267 ,  H01L29/66 ,  H01L29/06 ,  H01L29/22

CPC classification number: H01L29/7781 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/122 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66431 ,  H01L29/785

Abstract: Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness Tw sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

Abstract translation: 提供包括应变通道区域的集成电路器件及其形成方法。 集成电路器件可以包括增强型场效应晶体管。 增强型场效应晶体管可以包括具有足够的阱厚度Tw的量子阱沟道区，其足以产生其中的多个等效型电子传导状态的应变引起的分裂到相应的不等能级，包括与 当表面被偏置到反转状态时，邻近通道区域的表面的最低表面粗糙度散射。