公开(公告)号：US09734898B2

公开(公告)日：2017-08-15

申请号：US14308739

申请日：2014-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changkyu Seol ,  Junjin Kong ,  Hyejeong So ,  Hong Rak Son

IPC: G06F12/02 ,  G11C11/56

CPC classification number: G11C11/5621 ,  G06F12/0246 ,  G06F2212/72

Abstract: A memory controller includes a state shaping encoder that receives k-bit write data, selects a logical page with reference to state shape mapping information, and changes data of the logical page to decrease an occurrence probability of a high-order program state among program states used to program the k-bit data in multi-level memory cells.

公开(公告)号：US20250130891A1

公开(公告)日：2025-04-24

申请号：US18657360

申请日：2024-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghyeog Choi ,  Jiho Kim ,  Changkyu Seol ,  Yuseok Song ,  Daewook Kim

IPC: G06F11/10

Abstract: A memory system includes a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device includes a memory cell array that is divided into a plurality of sub array blocks arranged in a first direction and a second direction. The memory controller includes an error correction code (ECC) engine. The ECC engine, in a write operation, generates a parity data by performing an ECC encoding on a user data including a plurality of sub data units, generates a main data by interleaving the sub data units based on mapping information such that two sub data units to be stored in one row of a target sub array block are included in one symbol. The mapping information indicates a mapping relationship between the plurality of sub data units and rows of the target sub array block storing the plurality of sub data units.

公开(公告)号：US12100469B2

公开(公告)日：2024-09-24

申请号：US17962992

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsuk Woo ,  Sucheol Lee ,  Changkyu Seol

IPC: G11C7/10 ,  G11C7/04 ,  G11C7/14

CPC classification number: G11C7/1063 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/14

Abstract: A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.

公开(公告)号：US11942968B2

公开(公告)日：2024-03-26

申请号：US17975034

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu Seol ,  Sungrae Kim ,  Chisung Oh ,  Junghwan Choi

IPC: H03M13/00 ,  H03M5/14 ,  H04L1/00

CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0014

Abstract: A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

公开(公告)号：US20230377669A1

公开(公告)日：2023-11-23

申请号：US18134776

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyoung Choi ,  Gilyoung Kang ,  Sungrae Kim ,  Hyeran Kim ,  Jeongseok Park ,  Changkyu Seol

IPC: G11C29/36 ,  G11C29/14 ,  G11C29/38

CPC classification number: G11C29/36 ,  G11C29/14 ,  G11C29/38

Abstract: A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.

公开(公告)号：US11762558B2

公开(公告)日：2023-09-19

申请号：US16533883

申请日：2019-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggeon Yoo ,  Changkyu Seol ,  Hyeonwu Kim ,  Hyeongseok Song

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0614 ,  G06F3/0629 ,  G06F3/0688

Abstract: A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

公开(公告)号：US11526287B2

公开(公告)日：2022-12-13

申请号：US16828170

申请日：2020-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejeong So ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Jinsoo Lim ,  Jae Hun Jang ,  Seonghyeong Choi

IPC: G06F3/06 ,  G06N20/00 ,  G06F13/20 ,  G06N3/063

Abstract: A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.

公开(公告)号：US11362868B2

公开(公告)日：2022-06-14

申请号：US16911801

申请日：2020-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu Seol ,  Hongrak Son ,  Geunyeong Yu ,  Pilsang Yoon ,  Jaehun Jang

IPC: H04L27/04 ,  H04L1/00 ,  H04L27/06 ,  G06N3/063 ,  G06N3/04

Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.

公开(公告)号：US11216338B2

公开(公告)日：2022-01-04

申请号：US16835721

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjun Hwang ,  Dong-Min Shin ,  Changkyu Seol ,  Jaeyong Son ,  Hong Rak Son

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/10

Abstract: A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2m states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by “k” states (k being an integer greater than 2) smaller in number than the 2m states, performs first error correction encoding on the second write data to generate third write data expressed by the “k” states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.

公开(公告)号：US20210125048A1

公开(公告)日：2021-04-29

申请号：US16881963

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Pilsang Yoon ,  Junghyun Hong

IPC: G06N3/063 ,  G06N3/04 ,  G11C13/00

Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.