公开(公告)号：US08901724B2

公开(公告)日：2014-12-02

申请号：US12655335

申请日：2009-12-29

Applicant: John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

Inventor： John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

IPC: H01L23/02 ,  H01L23/12 ,  H01L23/053 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/56 ,  H01L25/03 ,  H01L21/683 ,  H01L23/538 ,  H05K1/18 ,  H01L25/10 ,  H05K3/46 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

公开(公告)号：US08896116B2

公开(公告)日：2014-11-25

申请号：US13736209

申请日：2013-01-08

Applicant: Ravi K. Nalla ,  Mathew J. Manusharow ,  Drew W. Delaney

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow ,  Drew W. Delaney

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83203 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底内的管芯（120），管芯具有前侧（121）和后侧（122）以及贯通硅通孔（123） 在模具的前侧构建的上层（130）和与模具的背面物理接触的动力平面（140）。 在另一个实施例中，微电子封装包括衬底（210），嵌入衬底中的第一裸片（220）和第二裸片（260），并具有正面（221,261）和背面（222,262） 和其中的穿硅通孔（223,263），在第一和第二模具的前侧上方的堆积层（230），以及与第一和第二模具的背面物理接触的导电结构（240） 和第二个死亡。

公开(公告)号：US20130228911A1

公开(公告)日：2013-09-05

申请号：US13848237

申请日：2013-03-21

Applicant: Mathew J. Manusharow ,  Ravi K. Nalla

Inventor： Mathew J. Manusharow ,  Ravi K. Nalla

IPC: H01L23/00

CPC classification number: H01L23/564 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1815 ,  H01L2924/18162

Abstract: A low-profile microelectronic package includes a die (110) (having a first surface (111) and a second surface (112)) and a package substrate (120). The substrate includes an electrically insulating layer (121) that forms a first side (126) of the substrate, an electrically conductive layer (122) connected to the die, and a protective layer (123) over the conductive layer that forms a second side (127) of the substrate. The first surface of the die is located at the first side of the substrate. The insulating layer has a plurality of pads (130) formed therein. The package further includes an array of interconnect structures (140) located at the first side of the substrate. Each interconnect structure in the array of interconnect structures has a first end (141) and a second end (142), and the first end is connected to one of the pads.

Abstract translation: 薄型微电子封装包括具有第一表面（111）和第二表面（112）的管芯（110）和封装衬底（120）。 衬底包括形成衬底的第一侧（126）的电绝缘层（121），连接到管芯的导电层（122）和形成第二侧的导电层上的保护层（123） （127）。 模具的第一表面位于基板的第一侧。 绝缘层具有形成在其中的多个焊盘（130）。 该封装还包括位于衬底第一侧的互连结构阵列（140）。 互连结构阵列中的每个互连结构具有第一端（141）和第二端（142），并且第一端连接到其中一个焊盘。

公开(公告)号：US20120139116A1

公开(公告)日：2012-06-07

申请号：US12962358

申请日：2010-12-07

Applicant: Mathew J. Manusharow ,  Mark S. Hlad ,  Ravi K. Nalla

Inventor： Mathew J. Manusharow ,  Mark S. Hlad ,  Ravi K. Nalla

IPC: H01L23/528 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/4641 ,  H01L2924/00

Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.

Abstract translation: 一种结构包括用于支撑半导体器件的混合衬底，该半导体器件包括其中嵌入半导体器件的无凸起积聚层和层叠芯结构。 通过与层压芯结构中的电镀通孔连接的无刷构建层结构的后续接合焊盘的加强电镀将无凸起的堆积层和层叠芯结构作为一体的装置。

公开(公告)号：US20110215464A1

公开(公告)日：2011-09-08

申请号：US12655335

申请日：2009-12-29

Applicant: John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

Inventor： John Stephen Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K. Nalla

IPC: H01L25/07 ,  H01L21/60

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract translation: 本发明的实施例描述了具有嵌入式管芯的半导体封装。 该半导体封装包括一个包含嵌入式裸片的无芯基板。 半导体封装提供管芯堆叠或封装堆叠功能。 此外，本发明的实施例描述了一种使组装成本最小化的半导体封装的制造方法。

公开(公告)号：US20090061232A1

公开(公告)日：2009-03-05

申请号：US12288933

申请日：2008-10-24

Applicant: Ravi K. Nalla

Inventor： Ravi K. Nalla

IPC: B32B17/00 ,  B01J19/08

CPC classification number: H01L21/563 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10T428/315 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include heating a portion of a ceramic substrate adjacent to a C4 area with a defocused laser, wherein a smooth region of the substrate is created, and applying an underfill material to the C4 area, wherein the underfill material does not extend past the smooth region.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括用散焦的激光器加热与C4区域相邻的陶瓷衬底的一部分，其中产生衬底的平滑区域，并将底部填充材料施加到C4区域，其中底部填充材料不延伸超过 平稳的地区。

公开(公告)号：US20080054047A1

公开(公告)日：2008-03-06

申请号：US11514824

申请日：2006-08-31

Applicant: Houssam Jomaa ,  Ravi K. Nalla ,  H. Ryan Chase

Inventor： Houssam Jomaa ,  Ravi K. Nalla ,  H. Ryan Chase

IPC: A47J36/02

CPC classification number: B23K3/0623 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/742 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/742 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: Microball delivery solutions for solder bumping are generally described. In this regard, according to one example embodiment, a microball delivery assembly includes a mask with at least two microball holder(s) to hold at least two different sizes of microball(s) that may correspond with at least two different-sized openings on a substrate, to provide simultaneous delivery of different-sized microballs upon a substrate.

Abstract translation: 通常描述用于焊料凸块的微球输送解决方案。 在这方面，根据一个示例性实施例，微球输送组件包括具有至少两个微球保持器的掩模，以保持至少两个不同尺寸的微球，其可对应于至少两个不同尺寸的开口， 基底，以提供不同尺寸的微球在基底上的同时传送。

公开(公告)号：US08508037B2

公开(公告)日：2013-08-13

申请号：US12962358

申请日：2010-12-07

Applicant: Mathew J. Manusharow ,  Mark S. Hlad ,  Ravi K. Nalla

Inventor： Mathew J. Manusharow ,  Mark S. Hlad ,  Ravi K. Nalla

IPC: H01L23/485

CPC classification number: H01L21/50 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/4641 ,  H01L2924/00

Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.

Abstract translation: 一种结构包括用于支撑半导体器件的混合衬底，该半导体器件包括其中嵌入半导体器件的无凸起积聚层和层叠芯结构。 通过与层压芯结构中的电镀通孔连接的无刷构建层结构的后续接合焊盘的加强电镀将无凸起的堆积层和层叠芯结构作为一体的装置。

公开(公告)号：US20130119544A1

公开(公告)日：2013-05-16

申请号：US13736209

申请日：2013-01-08

Applicant: Ravi K. Nalla ,  Mathew J. Manusharow ,  Drew W. Delaney

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow ,  Drew W. Delaney

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83203 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底内的管芯（120），管芯具有前侧（121）和后侧（122）以及贯通硅通孔（123） 在模具的前侧构建的上层（130）和与模具的背面物理接触的动力平面（140）。 在另一个实施例中，微电子封装包括衬底（210），嵌入衬底中的第一裸片（220）和第二裸片（260），并具有正面（221,261）和背面（222,262） 和其中的穿硅通孔（223,263），在第一和第二模具的前侧上方的堆积层（230），以及与第一和第二模具的背面物理接触的导电结构（240） 和第二个死亡。

公开(公告)号：US08183692B2

公开(公告)日：2012-05-22

申请号：US12835940

申请日：2010-07-14

Applicant: Ravi K. Nalla ,  Christine H. Tsau ,  Mark S. Hlad

Inventor： Ravi K. Nalla ,  Christine H. Tsau ,  Mark S. Hlad

IPC: H01L21/44

CPC classification number: H05K3/3484 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/244 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/29099

Abstract: A structure that may be used in substrate solder bumping comprises a substrate (110), a solder resist layer (120) disposed over the substrate, a plurality of solder resist openings (121) in a surface (122) of the solder resist layer, a conformal barrier layer (130) having a first portion (131) over the surface of the solder resist layer and a second portion (132) in the solder resist openings, a mask layer (140) over the first portion of the conformal barrier layer, and a solder material (150) in the solder resist openings over the metal layer. The conformal barrier layer acts as a barrier against interaction between the solder resist layer and the mask layer during solder reflow.

Abstract translation: 可用于衬底焊料凸块的结构包括衬底（110），设置在衬底上的阻焊层（120），在阻焊层的表面（122）中的多个阻焊剂开口（121） 具有在阻焊层的表面上的第一部分（131）和阻焊剂开口中的第二部分（132）的共形阻挡层（130），在保形阻挡层的第一部分之上的掩模层（140） ，以及在金属层上的阻焊剂开口中的焊料（150）。 在焊料回流期间，保形阻挡层用作防止阻焊层和掩模层之间的相互作用的屏障。