公开(公告)号：US09368566B2

公开(公告)日：2016-06-14

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US20160013125A1

公开(公告)日：2016-01-14

申请号：US14329646

申请日：2014-07-11

Applicant: QUALCOMM INCORPORATED

Inventor： Dong Wook Kim ,  Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01L23/498 ,  H05K3/28 ,  H05K3/46 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K3/284 ,  H05K3/46 ,  H05K2203/1316

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

Abstract translation: 一些新颖的特征涉及包括衬底，耦合到衬底的第一互连和围绕第一互连的第二互连的集成器件。 第二互连可以被配置为提供到地的电连接。 在一些实现中，第二互连包括板。 在一些实施方案中，集成器件还包括在第一互连和第二互连之间的介电材料。 在一些实施方案中，集成装置还包括围绕第二互连的模具。 在一些实现中，第一互连被配置为在第一方向上传导功率信号。 在一些实现中，第二互连被配置为在第二方向上传导接地信号。 在一些实施方式中，第二方向与第一方向不同。 在一些实施方式中，集成器件可以是封装封装（PoP）器件。

公开(公告)号：US20150311275A1

公开(公告)日：2015-10-29

申请号：US14791164

申请日：2015-07-02

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L49/02 ,  H01L23/498 ,  H01G4/012 ,  H01G4/30 ,  H01G4/12 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01G2/06 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/30 ,  H01G4/306 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L27/0805 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16267 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/014

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

公开(公告)号：US20150124418A1

公开(公告)日：2015-05-07

申请号：US14073756

申请日：2013-11-06

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Jonghae Kim

IPC: H05K1/16

CPC classification number: H05K1/165 ,  H05K1/141 ,  H05K2201/10378

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

Abstract translation: 提供了一种嵌入式分层电感器，其包括耦合到第一电感器层的第一电感器层和第二电感器层。 第一电感器层包括图案化的金属层，其也可以被图案化以形成焊盘。 第二电感器层包括沉积在邻近图案化金属层的电介质层中的金属。

公开(公告)号：US08987872B2

公开(公告)日：2015-03-24

申请号：US13794487

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L23/552 ,  H01L21/82 ,  H01L25/065 ,  H05K9/00 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/82 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K9/0007 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

Abstract translation: 一个特征涉及包括衬底和耦合到衬底的电磁干扰（EMI）屏蔽）的多芯片封装。 至少一个集成电路耦合到衬底的第一表面。 EMI屏蔽包括被配置为将封装与射频辐射屏蔽的金属外壳，耦合到金属外壳的内表面的至少一部分的电介质层和多个信号线。 信号线耦合到电介质层，并通过电介质层与金属外壳电隔离。 至少一个其它集成电路耦合到EMI屏蔽的内表面，并且EMI屏蔽的内表面的至少一部分面向基板的第一表面。 信号线被配置为向第二电路部件提供电信号。

公开(公告)号：US09812752B2

公开(公告)日：2017-11-07

申请号：US15218626

申请日：2016-07-25

Applicant: QUALCOMM Incorporated

Inventor： John Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01P1/20 ,  H01P7/06 ,  H01L21/00 ,  H01L27/15 ,  H01L23/66 ,  H01L49/02 ,  H03B5/18 ,  H01P1/201 ,  H01P1/207 ,  H01L23/552 ,  H01L21/48 ,  H01L23/522 ,  H01L23/60 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01P1/207 ,  H01L21/4853 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/10 ,  H01L2224/16227 ,  H01P1/201 ,  H01P7/06 ,  H01P7/065 ,  H03B5/1817 ,  H05K1/0243

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

公开(公告)号：US20170207022A1

公开(公告)日：2017-07-20

申请号：US15002174

申请日：2016-01-20

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  John Jong Hoon Lee ,  Sangjo Choi

IPC: H01F29/02 ,  G05B19/10 ,  H01F27/29 ,  H01F27/42 ,  G06F1/16 ,  H05K7/14

CPC classification number: H01F29/025 ,  G05B19/106 ,  G05B2219/25087 ,  G06F1/1633 ,  H01F27/29 ,  H01F27/42 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/645 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19042 ,  H05K1/141 ,  H05K1/165 ,  H05K3/3436 ,  H05K7/1485 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.

公开(公告)号：US09472425B2

公开(公告)日：2016-10-18

申请号：US14663342

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Jae Sik Lee

IPC: H01L21/48 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L21/4846 ,  H01G4/33 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3192 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L28/60 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/16238 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4661

Abstract: A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Abstract translation: 扇出晶片级封装结构可以包括多层再分配层（RDL）。 多层RDL可以被配置为与嵌入式电容器的端子耦合。 根据所选择的等效串联电阻（ESR）控制模式，多层RDL可以包括具有比多层RDL的其它部分更少的层的部分。

公开(公告)号：US20160183379A1

公开(公告)日：2016-06-23

申请号：US14579735

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Kyu-Pyung Hwang

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/185 ,  H01G4/224 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K2201/10015 ,  H05K2203/1469

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a base portion, a first terminal and a second terminal. The first terminal is located on a first surface of the base portion, where the first terminal is the only terminal on the first surface of the base portion. The second terminal is located on a second surface of the base portion. The second surface is opposite to the first surface. The second terminal is the only terminal on the second surface of the base portion. In some implementations, the capacitor further includes a first base metal layer located between the first surface of the base portion and the first terminal. In some implementations, the capacitor also includes a second base metal layer located between the second surface of the base portion and the second terminal.

Abstract translation: 一种衬底，其包括第一介电层和嵌入第一介电层中的电容器。 电容器包括基部，第一端子和第二端子。 第一端子位于基部的第一表面上，其中第一端子是基部的第一表面上的唯一端子。 第二端子位于基部的第二表面上。 第二表面与第一表面相对。 第二端子是基部的第二表面上的唯一端子。 在一些实施方式中，电容器还包括位于基部的第一表面和第一端之间的第一基底金属层。 在一些实施方式中，电容器还包括位于基部的第二表面和第二端之间的第二基底金属层。

公开(公告)号：US20160183378A1

公开(公告)日：2016-06-23

申请号：US14579651

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H01G4/012 ,  H05K3/40 ,  H01G4/30 ,  H01G4/248 ,  H05K1/11 ,  H05K3/30

CPC classification number: H05K1/185 ,  H01G4/005 ,  H01G4/012 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K3/30 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09781 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.

Abstract translation: 一种衬底，其包括第一介电层和嵌入第一介电层中的电容器。 电容器包括第一端子，第二端子和第三端子。 第二端子横向位于第一端子和第三端子之间。 电容器还包括第二电介质层，第一金属层和第二金属层。 第一金属层耦合到第一和第三端子。 第一金属层，第一端子和第三端子被配置成为第一信号提供第一电路径。 第二金属层耦合到第二端子。 第二金属层和第二端子被配置成为第二信号提供第二电路径。