知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

56 records (took 0.026 seconds)

    Write driver circuits for resistive random access memory (RAM) arrays
    23.
    发明授权
    Write driver circuits for resistive random access memory (RAM) arrays 有权
    为电阻随机存取存储器（RAM）阵列写入驱动电路

    公开(公告)号：US09583171B2

    公开(公告)日：2017-02-28

    申请号：US14644631

    申请日：2015-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79 ,  G11C2213/82

    Abstract: Aspects disclosed in the detailed description include write driver circuits for resistive random access memory (RAM) arrays. In one aspect, a write driver circuit is provided to facilitate writing data into a resistive RAM array in a memory system. The write driver circuit is coupled to a selector circuit configured to select a memory bitcell(s) in the resistive RAM array for a write operation. An isolation circuit is provided in the write driver circuit to couple a current source to the selector circuit to provide a write voltage during the write operation and to isolate the current source from the selector circuit when the selector circuit is not engaged in the write operation. By isolating the selector circuit from the current source when the selector circuit is on standby, it is possible to reduce leakage current in the selector circuit, thus reducing standby power consumption in the memory system.

    Abstract translation: 在详细描述中公开的方面包括用于电阻随机存取存储器（RAM）阵列的写入驱动器电路。 在一个方面，提供写入驱动器电路以便于将数据写入存储器系统中的电阻式RAM阵列。 写驱动器电路耦合到选择器电路，其被配置为选择用于写入操作的电阻RAM阵列中的存储器位单元。 在写入驱动器电路中提供隔离电路，以将电流源耦合到选择器电路以在写入操作期间提供写入电压，并且当选择器电路未被接合在写入操作中时将电流源与选择器电路隔离。 当选择器电路处于待机状态时，通过将选择器电路与电流源隔离，可以减少选择器电路中的漏电流，从而降低存储系统的待机功耗。

    Real time correction of bit failure in resistive memory
    24.
    发明授权
    Real time correction of bit failure in resistive memory 有权
    电阻存储器中位故障的实时校正

    公开(公告)号：US09552244B2

    公开(公告)日：2017-01-24

    申请号：US14150559

    申请日：2014-01-08

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Sungryul Kim ,  Jung Pill Kim

    IPC: G06F11/07 ,  H03M13/05 ,  G06F11/10 ,  G11C29/00 ,  G11C29/04

    CPC classification number: G06F11/0766 ,  G06F11/1008 ,  G11C29/808 ,  G11C29/814 ,  G11C2029/0411 ,  H03M13/05

    Abstract: Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.

    Abstract translation: 用于校正电阻存储器件中的位故障的系统和方法包括将存储器件划分成第一存储体和第二存储体。 第一单位修复（SBR）阵列存储在第二存储体中，其中第一SBR阵列被配置为在第一存储体的第一行中的第一故障位中存储故障的第一指示。 第一存储器组和第一SBR阵列被配置为在存储器访问操作期间并行访问。 类似地，存储在第一存储体中的第二SBR阵列可以存储位在第二存储体中的故障的指示，其中可以并行地访问第二SBR阵列和第二存储体。 因此，可以实时地校正第一和第二存储体中的位故障。

    PERFORMING MEMORY DATA SCRUBBING OPERATIONS IN PROCESSOR-BASED MEMORY IN RESPONSE TO PERIODIC MEMORY CONTROLLER WAKE-UP PERIODS
    26.
    发明申请
    PERFORMING MEMORY DATA SCRUBBING OPERATIONS IN PROCESSOR-BASED MEMORY IN RESPONSE TO PERIODIC MEMORY CONTROLLER WAKE-UP PERIODS 有权
    在基于处理器的存储器中对存储器控制器唤醒周期进行响应的存储器数据存储器操作

    公开(公告)号：US20160246679A1

    公开(公告)日：2016-08-25

    申请号：US14627268

    申请日：2015-02-20

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Sungryul Kim ,  Jung Pill Kim

    IPC: G06F11/14 ,  G06F12/02

    CPC classification number: G06F11/1402 ,  G06F11/106 ,  G06F12/023 ,  G06F12/0238 ,  G06F2201/805 ,  G06F2212/7205 ,  Y02D10/13

    Abstract: Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

    Abstract translation: 本公开的方面涉及被配置为在基于处理器的存储器中执行存储器数据擦除操作的存储器数据擦除器电路，以响应于周期性存储器控制器唤醒周期提供数据错误校正。 执行存储器数据擦除以校正存储在存储器中的数据字中的错误。 存储器数据擦除在存储器中启动，以节省处理器空闲周期内的周期性存储器控制器唤醒周期的功率。 此外，在本文公开的某些方面，存储器数据洗涤器电路作为存储器系统中的存储器控​​制器外部的单独系统提供。 以这种方式，由于存储器数据擦除器电路能够独立于存储器控制器操作，并且在完成唤醒期间发出的存储器控​​制器访问命令之后，可以继续存储器数据擦除操作，从而能够进一步降低功耗。 并且内存控制器掉电。

    SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY
    27.
    发明申请
    SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY 有权
    电阻记忆体中的参考电平的系统和方法

    公开(公告)号：US20160125926A1

    公开(公告)日：2016-05-05

    申请号：US14992753

    申请日：2016-01-11

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

    Abstract: A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

    Abstract translation: 一种方法包括在电阻式存储器件中，基于第一有效参考电阻和第二有效参考电阻来确定平均有效参考电阻电平。 第一有效参考电阻基于电阻性存储器件的第一组参考单元，第二有效参考电阻基于电阻式存储器件的第二组参考单元。 该方法包括至少部分地基于平均有效参考电阻电平来修整参考电阻。 响应于确定第一有效参考电阻基本上不等于平均有效参考电阻电平，修整参考电阻包括修改与第一有效参考电阻相关联的一个或多个磁性隧道结装置的一个或多个状态。

    SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION
    29.
    发明申请
    SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION 有权
    感应放大器偏置电压降低

    公开(公告)号：US20150022264A1

    公开(公告)日：2015-01-22

    申请号：US13947144

    申请日：2013-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Daeik D. Kim

    IPC: G01R31/28 ,  H03F1/00

    CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

    Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

    Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。

    ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS
    30.
    发明申请
    ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS 审中-公开
    ROW-DECODER电路和双电源系统的方法

    公开(公告)号：US20130314980A1

    公开(公告)日：2013-11-28

    申请号：US13953780

    申请日：2013-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Seung H. Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1653 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

    Abstract: A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.

    Abstract translation: 旋转转矩磁性随机存取存储器包括具有用于读取操作的电荷共享的双电压行解码器。 具有用于读取操作的电荷共享的双电压行解码器可降低读取干扰故障率，并提供强大的宏设计，提高产量。 在写入操作期间可以应用来自其中一个电源的电压。

Patent Agency Ranking