公开(公告)号：US20150116965A1

公开(公告)日：2015-04-30

申请号：US14067677

申请日：2013-10-30

Applicant: Qualcomm Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Dong Wook Kim ,  Hong Bok We

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/18 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/11 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

Abstract translation: 一些新颖的特征涉及包括第一介电层和桥结构的基板。 桥结构嵌入在第一电介质层中。 桥结构构造成在第一管芯和第二管芯之间提供电连接。 第一和第二管芯被配置为耦合到衬底。 桥结构包括第一组互连和第二介电层。 第一组互连嵌入在第一介质层中。 在一些实现中，桥结构还包括第二组互连。 在一些实施方案中，第二介电层被嵌入在第一介电层中。 在一些实施方式中，第一介电层包括桥结构的第一组互连，桥结构中的第二组互连以及桥结构中的一组焊盘。

公开(公告)号：US20150084653A1

公开(公告)日：2015-03-26

申请号：US14038608

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Young K. Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: G01R27/02 ,  G01R31/28

CPC classification number: G01R27/02

Abstract: A method and apparatus for testing integrated circuit resistors includes applying a variable source current to a resistive device under test (DUT), measuring the resistance of the resistive DUT as a function of the source current, and fitting the measured resistance to parameters of a polynomial parametric equation, wherein the parametric equation comprises a constant resistance at zero current bias plus a second order current coefficient of resistance multiplied by the square of the current.

Abstract translation: 用于测试集成电路电阻的方法和装置包括将可变源电流施加到被测电阻器件（DUT），测量作为源电流的函数的电阻DUT的电阻，并将测得的电阻拟合到多项式的参数 参数方程式，其中参数方程包括零电流偏置处的恒定电阻加上电阻乘以电流平方的二阶电流电流系数。

公开(公告)号：US08987872B2

公开(公告)日：2015-03-24

申请号：US13794487

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L23/552 ,  H01L21/82 ,  H01L25/065 ,  H05K9/00 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/82 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K9/0007 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

Abstract translation: 一个特征涉及包括衬底和耦合到衬底的电磁干扰（EMI）屏蔽）的多芯片封装。 至少一个集成电路耦合到衬底的第一表面。 EMI屏蔽包括被配置为将封装与射频辐射屏蔽的金属外壳，耦合到金属外壳的内表面的至少一部分的电介质层和多个信号线。 信号线耦合到电介质层，并通过电介质层与金属外壳电隔离。 至少一个其它集成电路耦合到EMI屏蔽的内表面，并且EMI屏蔽的内表面的至少一部分面向基板的第一表面。 信号线被配置为向第二电路部件提供电信号。

公开(公告)号：US09466554B2

公开(公告)日：2016-10-11

申请号：US14274517

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L21/4763 ,  H01L23/48 ,  H01L23/50 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和衬垫的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：US09401350B1

公开(公告)日：2016-07-26

申请号：US14812476

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L25/18 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L21/52 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L21/52 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

Abstract translation: 公开了一种封装封装（POP）结构。 POP结构包括第一裸片，第二裸片和光成像电介质（PID）层。 PID层设置在第一管芯和第二管芯之间。 POP结构还包括从第一管芯通过PID层到第二管芯的第一导电路径。 第一导电路径直接在第一管芯和第二管芯之间直接延伸通过PID层的第一区域。 POP结构还包括从第一管芯通过PID层到第二管芯的第二导电路径。 第二导电路径的特定部分垂直于第一导电路径并且不直接在第一管芯和第二管芯之间延伸穿过PID层的第二区域。

公开(公告)号：US20160133571A1

公开(公告)日：2016-05-12

申请号：US14535966

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分配部分的集成器件封装。 封装部分包括第一管芯，耦合到第一管芯的第一组通孔，第二管芯，耦合到第二管芯的第二组通孔，桥接器和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一个模具。 桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分地封装第一管芯，第二管芯，桥接器，第一组通孔和第二组通孔。 再分配部分耦合到封装部分。 再分配部分包括一组再分布互连和至少一个电介质层。

公开(公告)号：US09230936B2

公开(公告)日：2016-01-05

申请号：US14196817

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.

Abstract translation: 一些新颖的特征涉及一种集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一管芯以及第一管芯和基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电耦合第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。

公开(公告)号：US20150325375A1

公开(公告)日：2015-11-12

申请号：US14272356

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01G4/30 ,  H05K3/46 ,  H05K1/11 ,  H01G2/02 ,  H05K1/18

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：US20150294791A1

公开(公告)日：2015-10-15

申请号：US14252695

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Hong Bok We ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01G4/30 ,  H05K1/18 ,  H01G4/005 ,  H05K1/02 ,  H01L23/00 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/232 ,  H01G4/33 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/32265 ,  H01L2224/83801 ,  H01L2924/1205 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10515

Abstract: A ceramic capacitor is provided that includes a first capacitor surface, a second opposing capacitor surface, and metal plates perpendicular to the first capacitor surface and second opposing capacitor surface. The metal plates extend from the first capacitor surface to the second opposing capacitor surface. The ceramic capacitor is capable of being interposed between a die and a substrate. A portion of the metal plates are capable of being coupled to conductive pads of the die on the first capacitor surface and to conductive pads of the substrate on the second capacitor surface.

Abstract translation: 提供一种陶瓷电容器，其包括第一电容器表面，第二相对电容器表面和垂直于第一电容器表面和第二相对电容器表面的金属板。 金属板从第一电容器表面延伸到第二相对的电容器表面。 陶瓷电容器能够插入在管芯和衬底之间。 金属板的一部分能够耦合到第一电容器表面上的管芯的导电焊盘和第二电容器表面上的衬底的导电焊盘。

公开(公告)号：US20150214127A1

公开(公告)日：2015-07-30

申请号：US14162969

申请日：2014-01-24

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim

IPC: H01L23/367 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2924/1015 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a substrate. The substrate includes a first cavity (e.g., trench). The first cavity includes a first edge that is non-vertical. The first cavity is configured to align a die towards a center of the first cavity when the die is placed off-center of the first cavity. The integrated device also includes a first die positioned in the first cavity. The integrated device further includes a redistribution portion coupled to the first die. In some implementations, the first edge is a first wall of the first cavity. In some implementations, the first cavity includes a first opening and a first base portion. The first opening of the first cavity is greater than the first base portion of the first cavity.

Abstract translation: 一些特征涉及包括基板的集成装置。 衬底包括第一腔（例如沟槽）。 第一腔包括非垂直的第一边缘。 第一腔被配置成当模具被放置在第一腔体的中心以下时将模具朝着第一空腔的中心对准。 集成装置还包括位于第一腔中的第一模具。 集成器件还包括耦合到第一管芯的再分配部分。 在一些实施方式中，第一边缘是第一腔的第一壁。 在一些实施方式中，第一腔包括第一开口和第一基部。 第一腔的第一开口大于第一腔的第一基部。