公开(公告)号：US11658180B2

公开(公告)日：2023-05-23

申请号：US17188961

申请日：2021-03-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Shigeki Koya ,  Yasunari Umemoto ,  Takayuki Tsutsui

IPC: H01L27/082 ,  H01L23/00 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L23/498 ,  H01L21/8252 ,  H03F3/20 ,  H03F1/56

CPC classification number: H01L27/0823 ,  H01L21/8252 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L29/205 ,  H01L29/66318 ,  H01L29/7304 ,  H01L29/7371 ,  H01L2223/6655 ,  H01L2224/11462 ,  H01L2224/13019 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/16227 ,  H01L2224/81815 ,  H03F1/56 ,  H03F3/20 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

公开(公告)号：US11495563B2

公开(公告)日：2022-11-08

申请号：US16994187

申请日：2020-08-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao Kondo ,  Kenji Sasaki ,  Shigeki Koya ,  Shinnosuke Takahashi

IPC: H01L23/00 ,  H03F1/56 ,  H03F3/20

Abstract: Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.

公开(公告)号：US10741680B2

公开(公告)日：2020-08-11

申请号：US16710957

申请日：2019-12-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L21/00 ,  H01L29/737 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L21/306

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

公开(公告)号：US20180240899A1

公开(公告)日：2018-08-23

申请号：US15898440

申请日：2018-02-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/66242

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

公开(公告)号：US12040323B2

公开(公告)日：2024-07-16

申请号：US17394252

申请日：2021-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shaojun Ma ,  Shigeki Koya ,  Kenji Sasaki

IPC: H01L27/06 ,  H01L29/737 ,  H03F3/19 ,  H03F3/21

CPC classification number: H01L27/0647 ,  H01L29/737 ,  H03F3/19 ,  H03F3/21

Abstract: Each of cells arranged on a substrate surface along a first direction includes at least one unit transistor. Collector electrodes are arranged between two adjacent cells. A first cell, which is at least one of the cells, includes unit transistors arranged along the first direction. The unit transistors are connected in parallel to each another. In the first cell, the base electrode and the emitter electrode in each unit transistor are arranged along the first direction, and the order of arrangement of the base electrode and the emitter electrode is the same among the unit transistors. When looking at one first cell, a maximum value of distances in the first direction between the emitter electrodes of two adjacent unit transistors in the first cell being looked at is shorter than ½ of a shorter one of distances between the first cell being looked at and adjacent cells.

公开(公告)号：US11978786B2

公开(公告)日：2024-05-07

申请号：US17495588

申请日：2021-10-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Shigeki Koya ,  Masao Kondo ,  Takayuki Tsutsui

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L23/00 ,  H01L27/102 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/735 ,  H03F1/30 ,  H03F1/56 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H03F3/24

CPC classification number: H01L29/7371 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28575 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/31111 ,  H01L24/00 ,  H01L29/0813 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66318 ,  H03F1/56 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F3/245 ,  H01L29/452 ,  H03F1/302 ,  H03F2200/222 ,  H03F2200/267 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/451

Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

公开(公告)号：US11769702B2

公开(公告)日：2023-09-26

申请号：US17224784

申请日：2021-04-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Yoshimitsu Takenouchi ,  Kenji Sasaki ,  Masao Kondo

IPC: H01L23/13 ,  H05K1/02 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L24/13 ,  H05K1/0298 ,  H01L2224/1301 ,  H01L2224/1308 ,  H01L2924/14

Abstract: An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.

公开(公告)号：US11705875B2

公开(公告)日：2023-07-18

申请号：US17453962

申请日：2021-11-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Yasunari Umemoto ,  Yuichi Saito ,  Isao Obu ,  Takayuki Tsutsui

IPC: H03F3/21 ,  H03F1/02 ,  H01F17/00 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H03F3/213

CPC classification number: H03F3/211 ,  H01F17/0013 ,  H01L23/49822 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H03F1/0205 ,  H03F3/213 ,  H01F2017/008 ,  H01L24/13 ,  H01L2223/6644 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2924/3025 ,  H03F2200/114 ,  H03F2200/273 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/541 ,  H03F2203/21106 ,  H03F2203/21142

Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

公开(公告)号：US11610883B2

公开(公告)日：2023-03-21

申请号：US17149851

申请日：2021-01-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Takayuki Tsutsui ,  Kazuhito Nakai ,  Yusuke Tanaka

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

公开(公告)号：US11227941B2

公开(公告)日：2022-01-18

申请号：US16920324

申请日：2020-07-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L21/00 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L29/205

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.