公开(公告)号：US07149095B2

公开(公告)日：2006-12-12

申请号：US10281550

申请日：2002-10-28

申请人： Michael Warner ,  Philip Damberg ,  John B. Riley ,  David Gibson ,  Young-Gon Kim ,  Belgacem Haba ,  Vernon Solberg

发明人： Michael Warner ,  Philip Damberg ,  John B. Riley ,  David Gibson ,  Young-Gon Kim ,  Belgacem Haba ,  Vernon Solberg

IPC分类号： H05K1/11

CPC分类号： H05K1/189 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599

摘要： A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.

摘要翻译： 堆叠的微电子组件包括多个微电子子组件。 每个子组件包括具有至少一个位置，多个第一触点和多个第二触点的基板。 每个子组件还具有组装到至少一个附接位置并电连接到第一和第二触点中的至少一些的至少一个微电子元件。 折叠基板使得第一触头在子组件的底部可接近，并且第二触头可在子组件的顶部接近。 多个子组件以大致垂直的配置堆叠在另一个之上。 至少一个子组件的衬底具有多个附接位置和组装到附接位置的多个微电子元件。 折叠基板使得多个微电子元件中的至少一些彼此并排设置。

公开(公告)号：US06913949B2

公开(公告)日：2005-07-05

申请号：US10834342

申请日：2004-04-28

申请人： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell

发明人： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell

IPC分类号： H01L25/18 ,  H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/02 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L31/0336

CPC分类号： H01L23/528 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

摘要翻译： 堆叠式芯片组件包括具有安装在电介质层上的芯片的单独单元和在将芯片的触点与布置在电介质层的周边区域中的端子互连的电介质层上的迹线。 至少一些迹线是将分片选择触点连接到芯片选择端子的多分支迹线。 这些单元彼此堆叠，不同单元的相应端子通过焊球或其它导电元件彼此连接，以形成垂直总线。 在堆叠之前，单个单元的多分支迹线通过断开各个分支而被选择性地中断，以便将芯片的芯片选择触点留在连接到不同芯片选择端子的不同单元中，从而将这些芯片连接到不同的垂直 巴士 各个单元期望地是薄的并且直接地彼此邻接，以便提供具有来自堆叠内的芯片的良好热传递的低高度组件。

公开(公告)号：US6010058A

公开(公告)日：2000-01-04

申请号：US25110

申请日：1998-02-17

申请人： Young-Gon Kim ,  Dong-You Kim

发明人： Young-Gon Kim ,  Dong-You Kim

IPC分类号： B23K1/00 ,  H05K1/00 ,  H05K3/22 ,  H05K3/34 ,  B23K31/02

CPC分类号： H05K3/3436 ,  B23K1/0016 ,  H05K3/225 ,  B23K2201/42 ,  H05K1/0293 ,  H05K2201/0305 ,  H05K2201/09781 ,  H05K2203/0126 ,  H05K3/3484 ,  Y02P70/613

摘要： In a BGA package having electrically connected active balls and electrically disconnected dummy balls, the active balls are positioned in a radial direction at intervals of 90.degree. around the dummy balls. When a defect occurs in a solder joint, the package can be easily repaired by finding defective active ball; forming a repair hole by using a cutting means at a predetermined portion of the printed circuit board corresponding to a central position between the dummy ball and the defectively soldered active ball; inserting a solder paste injector into the repair hole to inject solder thereinto; and mutually connecting pad extensions of the dummy ball and the defective active ball with the injected solder. Therefore, the overall process can be simplified and its reliability can be improved.

摘要翻译： 在具有电连接的有源球和电气断开的虚拟球的BGA封装中，活动球围绕虚拟球以90度的间隔沿径向方向定位。 当焊接点发生缺陷时，可以通过发现有缺陷的活动球来容易地修复包装; 在所述印刷电路板的与所述虚拟球和所述缺陷焊接的活性球之间的中心位置对应的预定部分处使用切割装置形成修复孔; 将焊膏注入器插入修复孔中以将焊料注入其中; 以及用注入的焊料将虚拟球和有缺陷的活性球相互连接的焊盘延伸部。 因此，可以简化整体处理，提高其可靠性。

公开(公告)号：US08445998B1

公开(公告)日：2013-05-21

申请号：US12712170

申请日：2010-02-24

申请人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

发明人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.

摘要翻译： 半导体封装包括引线结构，其上安装半导体管芯，其中至少一些引线的至少一部分延伸到封装的轴线或轴线处，或跨越封装的轴线或轴线，以阻止封装的热诱导生长， 减小或最小化包装内的应变和与之相关的可靠性问题。

公开(公告)号：US07714415B2

公开(公告)日：2010-05-11

申请号：US11453216

申请日：2006-06-15

申请人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

发明人： Young-Gon Kim ,  Nikhil Vishwanath Kelkar ,  Louis Elliott Pflughaupt

IPC分类号： H01L23/495 ,  H01L23/02

CPC分类号： H01L23/4951 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.

摘要翻译： 半导体封装包括引线结构，其上安装半导体管芯，其中至少一些引线的至少一部分延伸到封装的轴线或轴线处，或跨越封装的轴线或轴线，以阻止封装的热诱导生长， 减小或最小化包装内的应变和与之相关联的可靠性。

公开(公告)号：US20080042274A1

公开(公告)日：2008-02-21

申请号：US11975996

申请日：2007-10-23

申请人： Kyong-Mo Bang ,  David Gibson ,  Young-Gon Kim ,  John Riley

发明人： Kyong-Mo Bang ,  David Gibson ,  Young-Gon Kim ,  John Riley

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

摘要翻译： 包括底部单元半导体芯片的底部单元安装到电路板，并且诸如封装半导体芯片的一个或多个顶部元件安装到底部单元。 可以使用与将组件安装到电路板上通常使用的相同的技术来执行两种安装操作。 通常的封装芯片可以用作顶部元件，从而降低组装成本，并允许通过选择封装的芯片来定制组件。 该组件实现了与使用预组装的堆叠芯片单元获得的效果相似的优点，但是不包含包装在封装芯片中的裸芯片的特殊处理费用。

公开(公告)号：US20070138607A1

公开(公告)日：2007-06-21

申请号：US11648052

申请日：2006-12-28

申请人： Ilyas Mohammed ,  Young-Gon Kim

发明人： Ilyas Mohammed ,  Young-Gon Kim

IPC分类号： H01L23/495

CPC分类号： H01L23/4985 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00

摘要： A lead assembly including a connector connecting structure having a plurality of separable portions and a plurality of leads. Each of the leads defined that they have a first end, a second end, a lead axis defined by the first and the second end, and an offset portion disposed between the first end and the second end. The offset portion being offset from the lead axis and adapted to be displaced downwardly with respect to the lead axis and bonded to a contact. The leads are preferably integral with the connecting structure. The connecting structure may be arranged outwardly of the leads, or may include parts interdispersed between groups of leads. The groups of leads may or may not correspond to individual units incorporating a microelectronic element.

摘要翻译： 一种引线组件，包括具有多个可分离部分和多个引线的连接器连接结构。 引线中的每一个限定为它们具有由第一端和第二端限定的第一端，第二端和引线轴以及设置在第一端和第二端之间的偏移部分。 偏移部分从引导轴线偏移并且适于相对于引导轴向下移位并且接合到触点。 引线优选与连接结构成一体。 连接结构可以布置在引线的外部，或者可以包括在引线组之间分散的部分。 引线组可以或可以不对应于结合微电子元件的单个单元。

公开(公告)号：US07061122B2

公开(公告)日：2006-06-13

申请号：US10683097

申请日：2003-10-10

申请人： Young-Gon Kim ,  David Gibson ,  Michael Warner ,  Philip Damberg ,  Philip Osborn

发明人： Young-Gon Kim ,  David Gibson ,  Michael Warner ,  Philip Damberg ,  Philip Osborn

IPC分类号： H01L29/40

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647

摘要： An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

摘要翻译： 具有独立测试和修复功能的超薄系统级封装（SIP）包括：插入器，其布置在其顶表面和底表面上，多个封装的半导体芯片通过焊料凸块安装，根据Land Grid Array （LGA）格式，并且其中在SIP上不使用底部填充物。

公开(公告)号：US06977440B2

公开(公告)日：2005-12-20

申请号：US10454029

申请日：2003-06-04

申请人： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell ,  Wael Zohni ,  Ilyas Mohammed

发明人： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell ,  Wael Zohni ,  Ilyas Mohammed

IPC分类号： H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/02 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/528 ,  H01L23/66 ,  H01L25/065 ,  H01L31/0336 ,  H05K1/02

CPC分类号： H01L23/528 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/78301 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00014

摘要： A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

摘要翻译： 堆叠式芯片组件包括具有安装在电介质层上的芯片的单独单元和在将芯片的触点与布置在电介质层的周边区域中的端子互连的电介质层上的迹线。 至少一些迹线是将分片选择触点连接到芯片选择端子的多分支迹线。 这些单元彼此堆叠，不同单元的相应端子通过焊球或其它导电元件彼此连接，以形成垂直总线。 在堆叠之前，通过形成焊接桥，各个单元的多分支迹线被选择性地连接，以便在连接到不同的芯片选择端子的不同单元中留下芯片的芯片选择触点，从而将这些芯片连接到不同的垂直总线 。 各个单元期望地是薄的并且直接地彼此邻接，以便提供具有来自堆叠内的芯片的良好热传递的低高度组件。